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I tried to synthesize the F32C by cloning this repository, I adjusted the architecture to ARCH_RV32 and changed the debug parameter to true in the file altera/de0nano/top_bram.vhd and also changed it in generic/glue_bram.vhd`
Is there anything else that needs to be adjusted to synthesize the Risc-V F32C for a De0-Nano?
I did tests with the sof available on the website (http://www.nxlab.fer.hr/fpgarduino/de0nano.html) and apparently everything is fine, but when I try to synthesize locally with my Quartus II.
I'm using Quartus 13 Web Edition and De0-Nano, with Windows 10.
The text was updated successfully, but these errors were encountered:
Unraveling the project, which is wonderful and I have a lot to thank everyone involved, I realized that the pin configurations were not equivalent to what was stated on the official page.
I edited the file and corrected the port mapping, now being successful.
The problem of LEDs 0 to 2 reported in the Issue #94 still remains.
I tried to synthesize the F32C by cloning this repository, I adjusted the architecture to ARCH_RV32 and changed the debug parameter to true in the file
altera/de0nano/top_bram.vhd and also changed it in
generic/glue_bram.vhd`Is there anything else that needs to be adjusted to synthesize the Risc-V F32C for a De0-Nano?
I did tests with the
sof
available on the website (http://www.nxlab.fer.hr/fpgarduino/de0nano.html) and apparently everything is fine, but when I try to synthesize locally with my Quartus II.I'm using Quartus 13 Web Edition and De0-Nano, with Windows 10.
The text was updated successfully, but these errors were encountered: