{"payload":{"header_redesign_enabled":false,"results":[{"id":"213212597","archived":false,"color":"#b2b7f8","followers":0,"has_funding_file":false,"hl_name":"david-xhk/full_adder_tester","hl_trunc_description":"Mojo FPGA tester for our DIY full adder","language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":213212597,"name":"full_adder_tester","owner_id":37938921,"owner_login":"david-xhk","updated_at":"2019-10-07T09:29:14.253Z","has_issues":true}},"sponsorable":false,"topics":[],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":70,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Adavid-xhk%252Ffull_adder_tester%2B%2Blanguage%253AVerilog","metadata":null,"csrf_tokens":{"/david-xhk/full_adder_tester/star":{"post":"0iRW4AEYZkXPREhWnQVL_nMhnF59cA7a7ueKaDSzEU1wNx0BvxZb0lZ3sRTTgTUQ82PyNynBfiByXeb273fdgw"},"/david-xhk/full_adder_tester/unstar":{"post":"S4frz8z1Ym1XxU154LV_lwa4GEr1in6hF2UaxEpJHzYzPHWC4YIemUYugmiRxfCQFsfJhQUzaVgT_B9RA1fiHQ"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"XyNx6uOYwdbX8pMOFjcBR63cg9qp8JhQWPNeUEuJANhxxgH9mLNhlUO-hBHhFFPrhgAEJLVukM_6sFIHuJq5Ng"}}},"title":"Repository search results"}