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Verible formatter fails when third line of port list is blank #2182
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formatter
Verilog code formatter issues
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Trying this out with some more examples, it seems to be related to the blank line after the first two arguments, and not related to the comments: Something like this seems to fail to format: module my_module (
input logic a
, input logic b
, output c
, output d
);
endmodule While putting the blank line either between a and b or between c and d both work: module my_module (
input logic a
, input logic b
, output c
, output d
);
endmodule module my_module (
input logic a
, input logic b
, output c
, output d
);
endmodule |
paul-demo
changed the title
Verible formatter fails to handle comma-at-beginning-of-line style and/or inline comments
Verible formatter fails when third line of parameter list is blank
May 16, 2024
paul-demo
changed the title
Verible formatter fails when third line of parameter list is blank
Verible formatter fails when third line of parentheses list is blank
May 16, 2024
paul-demo
changed the title
Verible formatter fails when third line of parentheses list is blank
Verible formatter fails when third line of port list is blank
May 16, 2024
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v0.0-3454-g7fdc2876
Commit 2023-12-20
Built 2023-12-20T15:18:36Z
Test case
Actual output
OR
Expected output
Verible should obviously do some cleanup for this, and when one of the changes listed below is performed, it produces this:
Verible fails to format the input file atop this report, unless any of the following changes is made to the source code:
clk_pl_100
// another comment
It's very unusual -- something is clearly tripping up verible in this simplified example.
The text was updated successfully, but these errors were encountered: