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Verible formatter fails when third line of port list is blank #2182

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paul-demo opened this issue May 16, 2024 · 1 comment
Open

Verible formatter fails when third line of port list is blank #2182

paul-demo opened this issue May 16, 2024 · 1 comment
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formatter Verilog code formatter issues

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@paul-demo
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paul-demo commented May 16, 2024

v0.0-3454-g7fdc2876
Commit 2023-12-20
Built 2023-12-20T15:18:36Z

Test case

module my_module (
        input   logic                           clk_pl_100 // a comment
    , input   logic                          aresetn // another comment

    , output a
    , output b
    );
endmodule

Actual output

Already formatted, no change.

OR

Re-formatted text does not match formatted text; formatting failed to converge!  Please file a bug.

Expected output
Verible should obviously do some cleanup for this, and when one of the changes listed below is performed, it produces this:

module my_module (
      input  logic clk_pl_100  // a comment
    , input  logic aresetn     // another comment
    , output       a
    , output       b
);
endmodule

Verible fails to format the input file atop this report, unless any of the following changes is made to the source code:

  1. I remove an underscore from clk_pl_100
  2. I remove the blank line in the input list
  3. I remove the inline comment // another comment

It's very unusual -- something is clearly tripping up verible in this simplified example.

@paul-demo paul-demo added the formatter Verilog code formatter issues label May 16, 2024
@paul-demo
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Trying this out with some more examples, it seems to be related to the blank line after the first two arguments, and not related to the comments:

Something like this seems to fail to format:

module my_module (
        input   logic                           a
    , input   logic                          b

    , output c
    , output d
    );
endmodule

While putting the blank line either between a and b or between c and d both work:

module my_module (
        input   logic                           a

    , input   logic                          b
    , output c
    , output d
    );
endmodule
module my_module (
        input   logic                           a
    , input   logic                          b
    , output c

    , output d
    );
endmodule

@paul-demo paul-demo changed the title Verible formatter fails to handle comma-at-beginning-of-line style and/or inline comments Verible formatter fails when third line of parameter list is blank May 16, 2024
@paul-demo paul-demo changed the title Verible formatter fails when third line of parameter list is blank Verible formatter fails when third line of parentheses list is blank May 16, 2024
@paul-demo paul-demo changed the title Verible formatter fails when third line of parentheses list is blank Verible formatter fails when third line of port list is blank May 16, 2024
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