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Long localparam
lines are not formatted
#2156
Labels
formatter
Verilog code formatter issues
Comments
Probably related: Test case module test;
localparam int unsigned
DigitCount = 2 ** DigitCountLg2,
SegmentCount = 7,
MaxReprNumber = 10 ** DigitCount - 1,
BcdCount = $clog2(10);
endmodule Actual output module test;
localparam int unsigned
DigitCount = 2 ** DigitCountLg2,
SegmentCount = 7,
MaxReprNumber = 10 ** DigitCount - 1,
BcdCount = $clog2(
10
);
endmodule Expected or suggested output module test;
localparam int unsigned
DigitCount = 2 ** DigitCountLg2,
SegmentCount = 7,
MaxReprNumber = 10 ** DigitCount - 1,
BcdCount = $clog2(10);
endmodule |
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Test case
version: 3624 d256d77
Actual output
Same. If the long line is removed, the line is formatted to a single line though.
Expected or suggested output
I could not find any reference to the formatting of this style of many parameters in a single
localparam
statement in the style guides I searched for.I can create a PR if a fix is needed.
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