Precompiled AVX512 binary not working for Zen 4 Genoa

[nr23730]

When launching bwa-mem2 on a Zen 4 Epyc system the following error message will be displayed:

./bwa-mem2
Looking to launch executable "/opt/bwa-mem2/./bwa-mem2.avx512bw", simd = .avx512bw
Launching executable "/opt//bwa-mem2/./bwa-mem2.avx512bw"

Please verify that both the operating system and the processor support Intel(R) X87, CMOV, MMX, FXSAVE, SSE, SSE2, SSE3, SSSE3, SSE4_1, SSE4_2, MOVBE, POPCNT, F16C, AVX, FMA, BMI, LZCNT, AVX2, AVX512DQ, AVX512F, ADX, AVX512CD, AVX512BW, AVX512VL and CLWB instructions.

Manually launching other binaries, like AVX2 works just fine. Also compiling on the Zen 4 system (using gcc, I didn't try intel) solved the issue for me.

[fredjarlier]

Does the alignment works when compile with gcc in avx512 and avx2 please?

[nr23730]

Yes. This really seems related to the version of the Intel compiler that was used to build the precompiled binaries.

[fredjarlier]

Indeed thanks for your answer.

[sanchit-misra]

That's quite likely. Zen 4 Genoa didn't exist when these binaries were compiled :)

[fo40225]

I have built the binary, please check the result first before using it.

https://github.com/fo40225/bwa-mem2/releases/tag/v2.2.1-opt

[nr23730]

That's quite likely. Zen 4 Genoa didn't exist when these binaries were compiled :)

Yeah, but as they only added additional instructions sets, I wonder why it worked on Zen 3.

@fo40225 Thank you very much! Using the AMD compiler of course makes much sense in this case. However, even with your build using a recent version of the Intel compiler I stell get the same error.

[fo40225]

Because I'm using the -x parameter of the Intel compiler to generate the executable, the executable generated with the -x parameter checks the CPU brand before execution. If it's not an Intel CPU, it refuses to run. To avoid this behavior, you need to switch to using -march=, but I'm not sure if the optimization effects will be the same.

To maximize program execution performance on processors, you should use the latest AMD compiler with the -march=native parameter for AMD processors and the latest Intel compiler with the -xHOST parameter for Intel processors. This way, you can utilize all the instruction sets and features of the processor and optimize the instruction scheduling for instruction latency, pipeline depth, and cache size.

If you want to generate a generic executable, you should use GCC or Clang and specify -march=x86-64, or -march=x86-64-v2, or -march=x86-64-v3, or -march=x86-64-v4 to set the instruction set support level.

Ref.
https://www.agner.org/optimize/blog/read.php?i=49
https://www.agner.org/forum/viewtopic.php?f=1&t=6

https://www.intel.com/content/www/us/en/docs/dpcpp-cpp-compiler/developer-guide-reference/2023-2/march.html
https://www.intel.com/content/www/us/en/docs/dpcpp-cpp-compiler/developer-guide-reference/2023-2/mauto-arch-qauto-arch.html
https://www.intel.com/content/www/us/en/docs/dpcpp-cpp-compiler/developer-guide-reference/2023-2/mtune-tune.html
https://www.intel.com/content/www/us/en/docs/dpcpp-cpp-compiler/developer-guide-reference/2023-2/x-qx.html
https://www.intel.com/content/www/us/en/docs/dpcpp-cpp-compiler/developer-guide-reference/2023-2/ax-qax.html
https://www.intel.com/content/www/us/en/docs/dpcpp-cpp-compiler/developer-guide-reference/2023-2/xhost-qxhost.html

https://gcc.gnu.org/onlinedocs/gcc/x86-Options.html