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Multi-clock domain support incomplete #93
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johanpel
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Multi-clock domain support incomplete
[Hardware] Multi-clock domain support incomplete
Jul 9, 2019
mbrobbel
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[Hardware] Multi-clock domain support incomplete
Multi-clock domain support incomplete
Aug 28, 2019
mbrobbel
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hardware
Hardware related issue
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lang:vhdl
VHDL related issue
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Aug 28, 2019
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Writers currently do not properly support separate clock domains for the bus and accellerator, despite availability of separate clock/reset ports. The read side should support it, though enabling the CDC logic is inconveniently done for each reader separately through the CFG string. Multi-clock-domain test code should also be created or improved.
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