diff --git a/boards/Arty-Z7-10/spyn/__init__.py b/boards/Arty-Z7-10/spyn/__init__.py deleted file mode 100644 index a901dcc..0000000 --- a/boards/Arty-Z7-10/spyn/__init__.py +++ /dev/null @@ -1,36 +0,0 @@ -# Copyright (c) 2018, Xilinx, Inc. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# 1. Redistributions of source code must retain the above copyright notice, -# this list of conditions and the following disclaimer. -# -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# -# 3. Neither the name of the copyright holder nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR -# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; -# OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR -# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - - -__author__ = "KV Thanjavur Bhaaskar, Naveen Purushotham" -__copyright__ = "Copyright 2018, Xilinx" -__email__ = "kvt@xilinx.com, npurusho@xilinx.com" - -from .spyn import SpynOverlay - diff --git a/boards/Arty-Z7-10/spyn/spyn.bit b/boards/Arty-Z7-10/spyn/spyn.bit index ec4e5c8..1628d5a 100644 Binary files a/boards/Arty-Z7-10/spyn/spyn.bit and b/boards/Arty-Z7-10/spyn/spyn.bit differ diff --git a/boards/Arty-Z7-10/spyn/spyn.hwh b/boards/Arty-Z7-10/spyn/spyn.hwh index 5345b37..e5b64ae 100644 --- a/boards/Arty-Z7-10/spyn/spyn.hwh +++ b/boards/Arty-Z7-10/spyn/spyn.hwh @@ -1,5 +1,5 @@  - + @@ -28,21 +28,19 @@ - - - - - + + + @@ -65,30 +63,31 @@ - + - - + - + - + - + - + - + - + + + - + - + @@ -141,290 +140,112 @@ - + - - - - - - - - - - - + + + + + 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@@ -7841,29 +7565,39 @@ - + - + - + - + - + - + - + - + - + - + + + + + + + + + + + @@ -7871,14 +7605,14 @@ - + - + - + - + @@ -7891,289 +7625,372 @@ - + - + - + - + - + + + + + + - + - + + + - + - + - + - + - + - + - + - + + - + - + - + - + - + - + - + - + - + - + - + - + + + + + + - + - + + + - + - + - + - + - + - + - + - + + - + - + - + - + - + - + + + + + + - + - + + + - + - + - + - + - + - + - + - + + - + - + - + - + - + - + - + - + - + - + - + - + + + + + + - + - + + + - + - + - + - + - + - + - + - + + - + - + - + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + - + - + - + - + - + - + - + - + - + + + + + + + + - - + + + - - - + + + + + + + - - - - - - - - - - + - - - - + - - + + - + + + - - - + + + + + + + + + + + + + + + + + @@ -8181,168 +7998,3846 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + 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+ - + - + - + - + - - - - - - - - - - - - - + - + - - - - - - - - - - - - - - - + - + - @@ -8676,110 +12056,14 @@ - + - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + diff --git a/boards/Arty-Z7-10/spyn/spyn.tcl b/boards/Arty-Z7-10/spyn/spyn.tcl index 391b0b0..a819aeb 100644 --- a/boards/Arty-Z7-10/spyn/spyn.tcl +++ b/boards/Arty-Z7-10/spyn/spyn.tcl @@ -37,6 +37,13 @@ if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { # To test this script, run the following commands from Vivado Tcl console: # source zsys_script.tcl + +# The design that will be created by this Tcl script contains the following +# module references: +# Phase_Test, my_2_3MUX, SOH3, SOH3 + +# Please add the sources of those modules before sourcing this Tcl script. + # If there is no project opened, this script will create a # project, but make sure you do not have an existing project # <./myproj/project_1.xpr> in the current working folder. @@ -156,13 +163,16 @@ proc create_hier_cell_FOC { parentCell nameHier } { current_bd_instance $hier_obj # Create interface pins - create_bd_intf_pin -mode Monitor -vlnv xilinx.com:interface:axis_rtl:1.0 SLOT_0_AXIS - create_bd_intf_pin -mode Monitor -vlnv xilinx.com:interface:axis_rtl:1.0 SLOT_0_AXIS1 - create_bd_intf_pin -mode Monitor -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis - create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_V - create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_V - create_bd_intf_pin -mode Monitor -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_V1 - create_bd_intf_pin -mode Monitor -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_V2 + create_bd_intf_pin -mode Monitor -vlnv xilinx.com:interface:axis_rtl:1.0 I_ab_Filtered_m + create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 I_ab_raw + create_bd_intf_pin -mode Monitor -vlnv xilinx.com:interface:axis_rtl:1.0 I_ab_raw_m + create_bd_intf_pin -mode Monitor -vlnv xilinx.com:interface:axis_rtl:1.0 I_alphabeta_m + create_bd_intf_pin -mode Monitor -vlnv xilinx.com:interface:axis_rtl:1.0 I_dq_m + create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 V_PWM + create_bd_intf_pin -mode Monitor -vlnv xilinx.com:interface:axis_rtl:1.0 V_PWM_m + create_bd_intf_pin -mode Monitor -vlnv xilinx.com:interface:axis_rtl:1.0 V_abc_m + create_bd_intf_pin -mode Monitor -vlnv xilinx.com:interface:axis_rtl:1.0 V_alphabeta_m + create_bd_intf_pin -mode Monitor -vlnv xilinx.com:interface:axis_rtl:1.0 V_dq_m # Create pins create_bd_pin -dir I -from 31 -to 0 Flux_Ki @@ -313,26 +323,29 @@ CONFIG.CONST_WIDTH {32} \ ] $torque_limit # Create interface connections - connect_bd_intf_net -intf_net Clarke_Direct_0_m_axis_V [get_bd_intf_pins Clarke_Direct_0/m_axis_V] [get_bd_intf_pins Park_Direct_0/s_axis_V] - connect_bd_intf_net -intf_net [get_bd_intf_nets Clarke_Direct_0_m_axis_V] [get_bd_intf_pins s_axis_V1] [get_bd_intf_pins Clarke_Direct_0/m_axis_V] connect_bd_intf_net -intf_net Clarke_Inverse_0_m_axis_V [get_bd_intf_pins Clarke_Inverse_0/m_axis_V] [get_bd_intf_pins SVPWM_0/s_axis_V] - connect_bd_intf_net -intf_net [get_bd_intf_nets Clarke_Inverse_0_m_axis_V] [get_bd_intf_pins SLOT_0_AXIS1] [get_bd_intf_pins Clarke_Inverse_0/m_axis_V] - connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins s_axis_V] [get_bd_intf_pins Filters_0/s_axis_V] - connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins m_axis_V] [get_bd_intf_pins SVPWM_0/m_axis_V] + connect_bd_intf_net -intf_net [get_bd_intf_nets Clarke_Inverse_0_m_axis_V] [get_bd_intf_pins V_abc_m] [get_bd_intf_pins Clarke_Inverse_0/m_axis_V] + connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins I_ab_raw] [get_bd_intf_pins Filters_0/s_axis_V] + connect_bd_intf_net -intf_net [get_bd_intf_nets Conn1] [get_bd_intf_pins I_ab_raw] [get_bd_intf_pins I_ab_raw_m] + connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins V_PWM] [get_bd_intf_pins SVPWM_0/m_axis_V] + connect_bd_intf_net -intf_net [get_bd_intf_nets Conn3] [get_bd_intf_pins V_PWM] [get_bd_intf_pins V_PWM_m] connect_bd_intf_net -intf_net Filters_0_m_axis_V [get_bd_intf_pins Clarke_Direct_0/s_axis_V] [get_bd_intf_pins Filters_0/m_axis_V] + connect_bd_intf_net -intf_net [get_bd_intf_nets Filters_0_m_axis_V] [get_bd_intf_pins I_ab_Filtered_m] [get_bd_intf_pins Filters_0/m_axis_V] connect_bd_intf_net -intf_net Flux_PI_Control_m_axis_V [get_bd_intf_pins Flux_PI_Control/m_axis_V] [get_bd_intf_pins foc_control_0/s_flux] connect_bd_intf_net -intf_net Park_Direct_0_m_axis_V [get_bd_intf_pins Park_Direct_0/m_axis_V] [get_bd_intf_pins axis_broadcaster_0/S_AXIS] - connect_bd_intf_net -intf_net [get_bd_intf_nets Park_Direct_0_m_axis_V] [get_bd_intf_pins SLOT_0_AXIS] [get_bd_intf_pins axis_broadcaster_0/S_AXIS] + connect_bd_intf_net -intf_net [get_bd_intf_nets Park_Direct_0_m_axis_V] [get_bd_intf_pins I_dq_m] [get_bd_intf_pins axis_broadcaster_0/S_AXIS] connect_bd_intf_net -intf_net Park_Inverse_0_m_axis_V [get_bd_intf_pins Clarke_Inverse_0/s_axis_V] [get_bd_intf_pins Park_Inverse_0/m_axis_V] - connect_bd_intf_net -intf_net [get_bd_intf_nets Park_Inverse_0_m_axis_V] [get_bd_intf_pins s_axis_V2] [get_bd_intf_pins Park_Inverse_0/m_axis_V] + connect_bd_intf_net -intf_net [get_bd_intf_nets Park_Inverse_0_m_axis_V] [get_bd_intf_pins V_alphabeta_m] [get_bd_intf_pins Park_Inverse_0/m_axis_V] connect_bd_intf_net -intf_net RPM_PI_Control_m_axis_V [get_bd_intf_pins RPM_PI_Control/m_axis_V] [get_bd_intf_pins foc_control_0/s_rpm] connect_bd_intf_net -intf_net Torque_PI_Control_m_axis_V [get_bd_intf_pins Torque_PI_Control/m_axis_V] [get_bd_intf_pins foc_control_0/s_torque] connect_bd_intf_net -intf_net axis_broadcaster_0_M00_AXIS [get_bd_intf_pins Flux_PI_Control/s_axis_V] [get_bd_intf_pins axis_broadcaster_0/M00_AXIS] connect_bd_intf_net -intf_net axis_broadcaster_0_M01_AXIS [get_bd_intf_pins Torque_PI_Control/s_axis_V] [get_bd_intf_pins axis_broadcaster_0/M01_AXIS] connect_bd_intf_net -intf_net axis_broadcaster_0_M02_AXIS [get_bd_intf_pins RPM_PI_Control/s_axis_V] [get_bd_intf_pins axis_broadcaster_0/M02_AXIS] connect_bd_intf_net -intf_net axis_broadcaster_0_M03_AXIS [get_bd_intf_pins axis_broadcaster_0/M03_AXIS] [get_bd_intf_pins foc_control_0/s_angle] + connect_bd_intf_net -intf_net axis_broadcaster_1_M01_AXIS [get_bd_intf_pins Clarke_Direct_0/m_axis_V] [get_bd_intf_pins Park_Direct_0/s_axis_V] + connect_bd_intf_net -intf_net [get_bd_intf_nets axis_broadcaster_1_M01_AXIS] [get_bd_intf_pins I_alphabeta_m] [get_bd_intf_pins Clarke_Direct_0/m_axis_V] connect_bd_intf_net -intf_net foc_control_0_m_axis [get_bd_intf_pins Park_Inverse_0/s_axis_V] [get_bd_intf_pins foc_control_0/m_axis] - connect_bd_intf_net -intf_net [get_bd_intf_nets foc_control_0_m_axis] [get_bd_intf_pins m_axis] [get_bd_intf_pins foc_control_0/m_axis] + connect_bd_intf_net -intf_net [get_bd_intf_nets foc_control_0_m_axis] [get_bd_intf_pins V_dq_m] [get_bd_intf_pins foc_control_0/m_axis] # Create port connections connect_bd_net -net Din1_1 [get_bd_pins RPM_Kp] [get_bd_pins RPM_Kp_slice/Din] @@ -371,6 +384,187 @@ CONFIG.CONST_WIDTH {32} \ current_bd_instance $oldCurInst } +# Hierarchical cell: FCSMPC +proc create_hier_cell_FCSMPC { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_FCSMPC() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode Monitor -vlnv xilinx.com:interface:axis_rtl:1.0 Idq_m + create_bd_intf_pin -mode Monitor -vlnv xilinx.com:interface:acc_handshake_rtl:1.0 ap_ctrl + + # Create pins + create_bd_pin -dir O -from 2 -to 0 GH + create_bd_pin -dir O GH_V_ap_vld + create_bd_pin -dir O -from 2 -to 0 GL + create_bd_pin -dir O -from 15 -to 0 Id_exp + create_bd_pin -dir O -from 15 -to 0 Id_out + create_bd_pin -dir O -from 15 -to 0 Iq_exp + create_bd_pin -dir O -from 15 -to 0 Iq_out + create_bd_pin -dir I -from 31 -to 0 -type data MPC_Control + create_bd_pin -dir I -from 15 -to 0 -type data angle + create_bd_pin -dir I -type clk ap_clk + create_bd_pin -dir I -type rst axis_in_aresetn + create_bd_pin -dir I -from 31 -to 0 -type data iq_SP + + # Create instance: AXI_to_Signal_0, and set properties + set AXI_to_Signal_0 [ create_bd_cell -type ip -vlnv mwn.de:user:AXI_to_Signal:1.0 AXI_to_Signal_0 ] + + # Create instance: FCSMPC_0, and set properties + set FCSMPC_0 [ create_bd_cell -type ip -vlnv TUM_EAL:hls:FCSMPC:3.0 FCSMPC_0 ] + + # Create instance: Iq_Sp_slice, and set properties + set Iq_Sp_slice [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 Iq_Sp_slice ] + set_property -dict [ list \ +CONFIG.DIN_FROM {15} \ +CONFIG.DOUT_WIDTH {16} \ + ] $Iq_Sp_slice + + # Create instance: MPC_Trigger_v1_0_0, and set properties + set MPC_Trigger_v1_0_0 [ create_bd_cell -type ip -vlnv TUM_EAL:user:MPC_Trigger_v1_0:1.0 MPC_Trigger_v1_0_0 ] + + # Create instance: P_sample, and set properties + set P_sample [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 P_sample ] + set_property -dict [ list \ +CONFIG.CONST_VAL {0x36d6bf95} \ +CONFIG.CONST_WIDTH {32} \ + ] $P_sample + + # Create instance: R_over_L, and set properties + set R_over_L [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 R_over_L ] + set_property -dict [ list \ +CONFIG.CONST_VAL {0x452ca6e5} \ +CONFIG.CONST_WIDTH {32} \ + ] $R_over_L + + # Create instance: SOH3_0, and set properties + set block_name SOH3 + set block_cell_name SOH3_0 + if { [catch {set SOH3_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $SOH3_0 eq "" } { + catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: SOH3_1, and set properties + set block_name SOH3 + set block_cell_name SOH3_1 + if { [catch {set SOH3_1 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $SOH3_1 eq "" } { + catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + + # Create instance: one_over_L, and set properties + set one_over_L [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 one_over_L ] + set_property -dict [ list \ +CONFIG.CONST_VAL {0x44960000} \ +CONFIG.CONST_WIDTH {32} \ + ] $one_over_L + + # Create instance: reset, and set properties + set reset [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 reset ] + set_property -dict [ list \ +CONFIG.CONST_VAL {0} \ + ] $reset + + # Create instance: xlslice_0, and set properties + set xlslice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 ] + set_property -dict [ list \ +CONFIG.DIN_FROM {15} \ +CONFIG.DOUT_WIDTH {16} \ + ] $xlslice_0 + + # Create instance: zeros, and set properties + set zeros [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 zeros ] + set_property -dict [ list \ +CONFIG.CONST_VAL {0} \ +CONFIG.CONST_WIDTH {16} \ + ] $zeros + + # Create interface connections + connect_bd_intf_net -intf_net Conn [get_bd_intf_pins Idq_m] [get_bd_intf_pins AXI_to_Signal_0/AXIS_IN] + connect_bd_intf_net -intf_net MPC_Trigger_v1_0_0_ap_ctrl [get_bd_intf_pins FCSMPC_0/ap_ctrl] [get_bd_intf_pins MPC_Trigger_v1_0_0/ap_ctrl] + connect_bd_intf_net -intf_net [get_bd_intf_nets MPC_Trigger_v1_0_0_ap_ctrl] [get_bd_intf_pins ap_ctrl] [get_bd_intf_pins MPC_Trigger_v1_0_0/ap_ctrl] + + # Create port connections + connect_bd_net -net AXI_to_Signal_0_Valid [get_bd_pins AXI_to_Signal_0/Valid] [get_bd_pins MPC_Trigger_v1_0_0/AXI_data_valid] + connect_bd_net -net FCSMPC_0_GH_V [get_bd_pins FCSMPC_0/GH_V] [get_bd_pins SOH3_1/Data] + connect_bd_net -net FCSMPC_0_GH_V_ap_vld [get_bd_pins GH_V_ap_vld] [get_bd_pins FCSMPC_0/GH_V_ap_vld] [get_bd_pins SOH3_1/Valid] + set_property -dict [ list \ +HDL_ATTRIBUTE.DEBUG {true} \ + ] [get_bd_nets FCSMPC_0_GH_V_ap_vld] + connect_bd_net -net FCSMPC_0_GL_V [get_bd_pins FCSMPC_0/GL_V] [get_bd_pins SOH3_0/Data] + connect_bd_net -net FCSMPC_0_GL_V_ap_vld [get_bd_pins FCSMPC_0/GL_V_ap_vld] [get_bd_pins SOH3_0/Valid] + connect_bd_net -net FCSMPC_0_id_exp [get_bd_pins Id_exp] [get_bd_pins FCSMPC_0/id_exp] + set_property -dict [ list \ +HDL_ATTRIBUTE.DEBUG {true} \ + ] [get_bd_nets FCSMPC_0_id_exp] + connect_bd_net -net FCSMPC_0_iq_exp [get_bd_pins Iq_exp] [get_bd_pins FCSMPC_0/iq_exp] + set_property -dict [ list \ +HDL_ATTRIBUTE.DEBUG {true} \ + ] [get_bd_nets FCSMPC_0_iq_exp] + connect_bd_net -net P_Controller_0_RPM [get_bd_pins AXI_to_Signal_0/Signal_47_32] [get_bd_pins FCSMPC_0/RPM] + connect_bd_net -net R_over_L_dout [get_bd_pins FCSMPC_0/R_over_L] [get_bd_pins R_over_L/dout] + connect_bd_net -net SOH3_0_Data_vld [get_bd_pins GL] [get_bd_pins SOH3_0/Data_vld] + connect_bd_net -net SOH3_1_Data_vld [get_bd_pins GH] [get_bd_pins SOH3_1/Data_vld] + connect_bd_net -net Torque_Sp_slice_Dout [get_bd_pins FCSMPC_0/iq_SP] [get_bd_pins Iq_Sp_slice/Dout] + connect_bd_net -net angle_1 [get_bd_pins angle] [get_bd_pins FCSMPC_0/angle] + connect_bd_net -net ap_clk_1 [get_bd_pins ap_clk] [get_bd_pins AXI_to_Signal_0/axis_in_aclk] [get_bd_pins FCSMPC_0/ap_clk] [get_bd_pins MPC_Trigger_v1_0_0/ap_clk] [get_bd_pins SOH3_0/clk] [get_bd_pins SOH3_1/clk] + connect_bd_net -net axis_in_aresetn_1 [get_bd_pins axis_in_aresetn] [get_bd_pins AXI_to_Signal_0/axis_in_aresetn] [get_bd_pins MPC_Trigger_v1_0_0/ap_rst] + connect_bd_net -net iq_SP_1 [get_bd_pins iq_SP] [get_bd_pins Iq_Sp_slice/Din] + connect_bd_net -net one_over_L1_1 [get_bd_pins MPC_Control] [get_bd_pins xlslice_0/Din] + connect_bd_net -net one_over_L1_dout [get_bd_pins FCSMPC_0/sampling_period] [get_bd_pins P_sample/dout] + connect_bd_net -net one_over_L_dout [get_bd_pins FCSMPC_0/one_over_L] [get_bd_pins one_over_L/dout] + connect_bd_net -net reset_dout [get_bd_pins FCSMPC_0/ap_rst] [get_bd_pins reset/dout] + connect_bd_net -net xlslice_0_Dout [get_bd_pins FCSMPC_0/lm_over_c_i_sqr] [get_bd_pins xlslice_0/Dout] + connect_bd_net -net xlslice_1_Dout [get_bd_pins Id_out] [get_bd_pins AXI_to_Signal_0/Signal_15_0] [get_bd_pins FCSMPC_0/id_m] + set_property -dict [ list \ +HDL_ATTRIBUTE.DEBUG {true} \ + ] [get_bd_nets xlslice_1_Dout] + connect_bd_net -net xlslice_2_Dout [get_bd_pins Iq_out] [get_bd_pins AXI_to_Signal_0/Signal_31_16] [get_bd_pins FCSMPC_0/iq_m] + set_property -dict [ list \ +HDL_ATTRIBUTE.DEBUG {true} \ + ] [get_bd_nets xlslice_2_Dout] + connect_bd_net -net zeros_dout [get_bd_pins FCSMPC_0/id_SP] [get_bd_pins zeros/dout] + + # Restore current instance + current_bd_instance $oldCurInst +} + # Procedure to create entire design; Provide argument to make # procedure reusable. If parentCell is "", will use root. @@ -408,7 +602,6 @@ proc create_root_design { parentCell } { set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ] # Create ports - set BTN0 [ create_bd_port -dir I BTN0 ] set ENC_A [ create_bd_port -dir I ENC_A ] set ENC_B [ create_bd_port -dir I ENC_B ] set ENC_I [ create_bd_port -dir I ENC_I ] @@ -419,12 +612,9 @@ proc create_root_design { parentCell } { set SDI2 [ create_bd_port -dir I SDI2 ] set SDI3 [ create_bd_port -dir I SDI3 ] set SDV [ create_bd_port -dir I SDV ] - set SW0 [ create_bd_port -dir I SW0 ] + set SW_0 [ create_bd_port -dir I SW_0 ] set led [ create_bd_port -dir O -from 3 -to 0 led ] - # Create instance: AXI_StreamCapture_0, and set properties - set AXI_StreamCapture_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:AXI_StreamCapture:1.0 AXI_StreamCapture_0 ] - # Create instance: Angle_RPM_Ib_Ia, and set properties set Angle_RPM_Ib_Ia [ create_bd_cell -type ip -vlnv trenz.biz:user:axis_concat:1.0 Angle_RPM_Ib_Ia ] set_property -dict [ list \ @@ -447,17 +637,37 @@ CONFIG.IN0_WIDTH {16} \ CONFIG.IN1_WIDTH {16} \ ] $Angle_concat + # Create instance: Decimate_Samples, and set properties + set Decimate_Samples [ create_bd_cell -type ip -vlnv trenz.biz:user:axis_decimate:1.0 Decimate_Samples ] + set_property -dict [ list \ +CONFIG.C_TDATA_WIDTH {64} \ + ] $Decimate_Samples + + # Create instance: FCSMPC + create_hier_cell_FCSMPC [current_bd_instance .] FCSMPC + # Create instance: FOC create_hier_cell_FOC [current_bd_instance .] FOC - # Create instance: Ib_Ia, and set properties - set Ib_Ia [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_subset_converter:1.1 Ib_Ia ] + # Create instance: I_a_Ib, and set properties + set I_a_Ib [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_subset_converter:1.1 I_a_Ib ] set_property -dict [ list \ CONFIG.M_TDATA_NUM_BYTES {4} \ CONFIG.S_TDATA_NUM_BYTES {8} \ CONFIG.TDATA_REMAP {tdata[31:0]} \ - ] $Ib_Ia - + ] $I_a_Ib + + # Create instance: Phase_Test_0, and set properties + set block_name Phase_Test + set block_cell_name Phase_Test_0 + if { [catch {set Phase_Test_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $Phase_Test_0 eq "" } { + catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + # Create instance: axi_datamover_0, and set properties set axi_datamover_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_datamover:5.1 axi_datamover_0 ] set_property -dict [ list \ @@ -478,63 +688,29 @@ CONFIG.c_s2mm_support_indet_btt {true} \ CONFIG.NUM_MI {1} \ ] $axi_interconnect_0 - # Create instance: axi_reg32_0, and set properties - set axi_reg32_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:axi_reg32:1.0 axi_reg32_0 ] - set_property -dict [ list \ -CONFIG.C_NUM_RO_REG {5} \ -CONFIG.C_NUM_WR_REG {16} \ -CONFIG.C_WR0_ALIAS {Control} \ -CONFIG.C_WR10_ALIAS {Angle Shift} \ -CONFIG.C_WR10_DEFAULT {719} \ -CONFIG.C_WR11_ALIAS {Vd} \ -CONFIG.C_WR11_DEFAULT {-7424} \ -CONFIG.C_WR12_ALIAS {Vq} \ -CONFIG.C_WR12_DEFAULT {15000} \ -CONFIG.C_WR13_ALIAS {Decimation} \ -CONFIG.C_WR14_ALIAS {TR_Control} \ -CONFIG.C_WR1_ALIAS {Flux Sp} \ -CONFIG.C_WR2_ALIAS {Flux Kp} \ -CONFIG.C_WR2_DEFAULT {-45056} \ -CONFIG.C_WR3_ALIAS {Flux Ki} \ -CONFIG.C_WR4_ALIAS {Torque Sp} \ -CONFIG.C_WR4_DEFAULT {100} \ -CONFIG.C_WR5_ALIAS {Torque Kp} \ -CONFIG.C_WR5_DEFAULT {256} \ -CONFIG.C_WR6_ALIAS {Torque Ki} \ -CONFIG.C_WR7_ALIAS {RPM Sp} \ -CONFIG.C_WR7_DEFAULT {3000} \ -CONFIG.C_WR8_ALIAS {RPM Kp} \ -CONFIG.C_WR8_DEFAULT {744} \ -CONFIG.C_WR9_ALIAS {RPM Ki} \ -CONFIG.C_WR9_DEFAULT {9} \ - ] $axi_reg32_0 - # Create instance: axis_AD7403_0, and set properties set axis_AD7403_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:axis_AD7403:1.0 axis_AD7403_0 ] set_property -dict [ list \ CONFIG.C_CLOCK_RATIO {5} \ -CONFIG.C_DECIMATION {128} \ +CONFIG.C_DECIMATION {32} \ CONFIG.C_SIGNED {true} \ ] $axis_AD7403_0 # Create instance: axis_data_fifo_0, and set properties set axis_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:1.1 axis_data_fifo_0 ] set_property -dict [ list \ -CONFIG.FIFO_DEPTH {4096} \ +CONFIG.FIFO_DEPTH {8192} \ +CONFIG.IS_ACLK_ASYNC {0} \ ] $axis_data_fifo_0 # Create instance: axis_data_fifo_1, and set properties set axis_data_fifo_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:1.1 axis_data_fifo_1 ] set_property -dict [ list \ -CONFIG.IS_ACLK_ASYNC {1} \ +CONFIG.ACLKEN_CONV_MODE {0} \ +CONFIG.FIFO_DEPTH {128} \ +CONFIG.IS_ACLK_ASYNC {0} \ ] $axis_data_fifo_1 - # Create instance: axis_decimate_0, and set properties - set axis_decimate_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:axis_decimate:1.0 axis_decimate_0 ] - set_property -dict [ list \ -CONFIG.C_TDATA_WIDTH {64} \ - ] $axis_decimate_0 - # Create instance: axis_encoder_0, and set properties set axis_encoder_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:axis_encoder:1.0 axis_encoder_0 ] set_property -dict [ list \ @@ -544,11 +720,11 @@ CONFIG.C_RPM_AXIS {true} \ CONFIG.C_USE_SHIFT {true} \ ] $axis_encoder_0 - # Create instance: axis_monitor_1, and set properties - set axis_monitor_1 [ create_bd_cell -type ip -vlnv trenz.biz:user:axis_monitor:1.1 axis_monitor_1 ] + # Create instance: axis_monitor_0, and set properties + set axis_monitor_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:axis_monitor:1.1 axis_monitor_0 ] set_property -dict [ list \ -CONFIG.C_SLAVE_IF {7} \ - ] $axis_monitor_1 +CONFIG.C_SLAVE_IF {8} \ + ] $axis_monitor_0 # Create instance: axis_pwm_0, and set properties set axis_pwm_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:axis_pwm:1.0 axis_pwm_0 ] @@ -559,30 +735,64 @@ CONFIG.C_IN_TYPE {1} \ CONFIG.C_S_AXIS_TDATA_WIDTH {64} \ ] $axis_pwm_0 - # Create instance: clk_mux_0, and set properties - set clk_mux_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:clk_mux:1.0 clk_mux_0 ] + # Create instance: capture_axi_PYNQ, and set properties + set capture_axi_PYNQ [ create_bd_cell -type ip -vlnv trenz.biz:user:AXI_StreamCapture:1.0 capture_axi_PYNQ ] - # Create instance: clk_wiz_0, and set properties - set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.4 clk_wiz_0 ] + # Create instance: control_axi_block, and set properties + set control_axi_block [ create_bd_cell -type ip -vlnv trenz.biz:user:axi_reg32:1.0 control_axi_block ] set_property -dict [ list \ -CONFIG.CLKOUT1_JITTER {236.910} \ -CONFIG.CLKOUT1_PHASE_ERROR {732.678} \ -CONFIG.CLKOUT1_REQUESTED_DUTY_CYCLE {50.0} \ -CONFIG.MMCM_BANDWIDTH {LOW} \ -CONFIG.MMCM_CLKFBOUT_MULT_F {21.000} \ -CONFIG.MMCM_CLKOUT0_DIVIDE_F {7.000} \ -CONFIG.MMCM_DIVCLK_DIVIDE {3} \ -CONFIG.USE_LOCKED {false} \ -CONFIG.USE_RESET {false} \ -CONFIG.USE_SPREAD_SPECTRUM {true} \ - ] $clk_wiz_0 +CONFIG.C_NUM_RO_REG {5} \ +CONFIG.C_NUM_WR_REG {16} \ +CONFIG.C_RR0_ALIAS {RR0_Angle} \ +CONFIG.C_RR1_ALIAS {RR1_RPM} \ +CONFIG.C_RR2_ALIAS {RR2_Id} \ +CONFIG.C_RR3_ALIAS {RR3_Iq} \ +CONFIG.C_WR0_ALIAS {Control} \ +CONFIG.C_WR10_ALIAS {Angle Shift} \ +CONFIG.C_WR10_DEFAULT {719} \ +CONFIG.C_WR11_ALIAS {Vd} \ +CONFIG.C_WR11_DEFAULT {-7424} \ +CONFIG.C_WR12_ALIAS {Vq} \ +CONFIG.C_WR12_DEFAULT {15000} \ +CONFIG.C_WR13_ALIAS {Decimation} \ +CONFIG.C_WR14_ALIAS {TR_Control} \ +CONFIG.C_WR1_ALIAS {Flux Sp} \ +CONFIG.C_WR2_ALIAS {Flux Kp} \ +CONFIG.C_WR2_DEFAULT {-45056} \ +CONFIG.C_WR3_ALIAS {Flux Ki} \ +CONFIG.C_WR4_ALIAS {Torque Sp} \ +CONFIG.C_WR4_DEFAULT {100} \ +CONFIG.C_WR5_ALIAS {Torque Kp} \ +CONFIG.C_WR5_DEFAULT {256} \ +CONFIG.C_WR6_ALIAS {Torque Ki} \ +CONFIG.C_WR7_ALIAS {RPM Sp} \ +CONFIG.C_WR7_DEFAULT {3000} \ +CONFIG.C_WR8_ALIAS {RPM Kp} \ +CONFIG.C_WR8_DEFAULT {744} \ +CONFIG.C_WR9_ALIAS {RPM Ki} \ +CONFIG.C_WR9_DEFAULT {9} \ + ] $control_axi_block + # Create instance: fit_timer_0, and set properties + set fit_timer_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:fit_timer:2.0 fit_timer_0 ] + set_property -dict [ list \ +CONFIG.C_NO_CLOCKS {1000} \ + ] $fit_timer_0 + + # Create instance: my_2_3MUX_0, and set properties + set block_name my_2_3MUX + set block_cell_name my_2_3MUX_0 + if { [catch {set my_2_3MUX_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } { + catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } elseif { $my_2_3MUX_0 eq "" } { + catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."} + return 1 + } + # Create instance: proc_sys_reset_0, and set properties set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ] - # Create instance: proc_sys_reset_1, and set properties - set proc_sys_reset_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_1 ] - # Create instance: processing_system7_0, and set properties set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ] set_property -dict [ list \ @@ -590,7 +800,7 @@ CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {650.000000} \ CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.096154} \ CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \ CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \ -CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {20.000000} \ +CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {10.000000} \ CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \ CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {50.000000} \ CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {108.333336} \ @@ -604,7 +814,7 @@ CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {108.333336} \ CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {650} \ CONFIG.PCW_ARMPLL_CTRL_FBDIV {26} \ CONFIG.PCW_CLK0_FREQ {100000000} \ -CONFIG.PCW_CLK1_FREQ {20000000} \ +CONFIG.PCW_CLK1_FREQ {10000000} \ CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1300.000} \ CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {50} \ CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {52} \ @@ -631,10 +841,10 @@ CONFIG.PCW_EN_UART1 {1} \ CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5} \ CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {2} \ CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {10} \ -CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {5} \ +CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {10} \ CONFIG.PCW_FCLK_CLK1_BUF {TRUE} \ CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \ -CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {20} \ +CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {10} \ CONFIG.PCW_FPGA_FCLK1_ENABLE {1} \ CONFIG.PCW_FTM_CTI_IN0 {} \ @@ -945,25 +1155,49 @@ CONFIG.PCW_USE_S_AXI_HP0 {1} \ # Create instance: ps7_0_axi_periph, and set properties set ps7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps7_0_axi_periph ] set_property -dict [ list \ -CONFIG.NUM_MI {2} \ +CONFIG.NUM_MI {3} \ ] $ps7_0_axi_periph - # Create instance: rpm_check_0, and set properties - set rpm_check_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:rpm_check:1.0 rpm_check_0 ] - - # Create instance: rx_fifo, and set properties - set rx_fifo [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:1.1 rx_fifo ] - set_property -dict [ list \ -CONFIG.FIFO_DEPTH {512} \ -CONFIG.TDATA_NUM_BYTES {8} \ - ] $rx_fifo - - # Create instance: tx_fifo, and set properties - set tx_fifo [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:1.1 tx_fifo ] + # Create instance: system_ila_0, and set properties + set system_ila_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:system_ila:1.0 system_ila_0 ] set_property -dict [ list \ -CONFIG.FIFO_DEPTH {512} \ -CONFIG.TDATA_NUM_BYTES {8} \ - ] $tx_fifo +CONFIG.ALL_PROBE_SAME_MU_CNT {2} \ +CONFIG.C_ADV_TRIGGER {false} \ +CONFIG.C_BRAM_CNT {5.5} \ +CONFIG.C_DATA_DEPTH {4096} \ +CONFIG.C_EN_STRG_QUAL {1} \ +CONFIG.C_MON_TYPE {MIX} \ +CONFIG.C_NUM_MONITOR_SLOTS {4} \ +CONFIG.C_NUM_OF_PROBES {8} \ +CONFIG.C_PROBE0_MU_CNT {2} \ +CONFIG.C_PROBE0_TYPE {0} \ +CONFIG.C_PROBE1_MU_CNT {2} \ +CONFIG.C_PROBE1_TYPE {0} \ +CONFIG.C_PROBE2_MU_CNT {2} \ +CONFIG.C_PROBE2_TYPE {0} \ +CONFIG.C_PROBE3_MU_CNT {2} \ +CONFIG.C_PROBE3_TYPE {0} \ +CONFIG.C_PROBE4_MU_CNT {2} \ +CONFIG.C_PROBE4_TYPE {0} \ +CONFIG.C_PROBE5_MU_CNT {2} \ +CONFIG.C_PROBE6_MU_CNT {2} \ +CONFIG.C_PROBE7_MU_CNT {2} \ +CONFIG.C_SLOT {0} \ +CONFIG.C_SLOT_0_APC_EN {0} \ +CONFIG.C_SLOT_0_AXI_DATA_SEL {1} \ +CONFIG.C_SLOT_0_AXI_TRIG_SEL {1} \ +CONFIG.C_SLOT_0_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \ +CONFIG.C_SLOT_1_APC_EN {0} \ +CONFIG.C_SLOT_1_AXI_DATA_SEL {1} \ +CONFIG.C_SLOT_1_AXI_TRIG_SEL {1} \ +CONFIG.C_SLOT_1_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \ +CONFIG.C_SLOT_2_APC_EN {0} \ +CONFIG.C_SLOT_2_AXI_DATA_SEL {1} \ +CONFIG.C_SLOT_2_AXI_TRIG_SEL {1} \ +CONFIG.C_SLOT_2_INTF_TYPE {xilinx.com:interface:axis_rtl:1.0} \ +CONFIG.C_SLOT_3_INTF_TYPE {xilinx.com:interface:acc_handshake_rtl:1.0} \ +CONFIG.C_SLOT_3_TYPE {0} \ + ] $system_ila_0 # Create instance: xlconcat_0, and set properties set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ] @@ -971,22 +1205,11 @@ CONFIG.TDATA_NUM_BYTES {8} \ CONFIG.NUM_PORTS {4} \ ] $xlconcat_0 - # Create instance: xlconcat_1, and set properties - set xlconcat_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_1 ] + # Create instance: xlconcat_2, and set properties + set xlconcat_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_2 ] set_property -dict [ list \ -CONFIG.IN0_WIDTH {4} \ -CONFIG.IN1_WIDTH {28} \ - ] $xlconcat_1 - - # Create instance: xlconstant_0, and set properties - set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] - set_property -dict [ list \ -CONFIG.CONST_VAL {0} \ -CONFIG.CONST_WIDTH {28} \ - ] $xlconstant_0 - - # Create instance: xlslice_0, and set properties - set xlslice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 ] +CONFIG.NUM_PORTS {4} \ + ] $xlconcat_2 # Create instance: xlslice_1, and set properties set xlslice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_1 ] @@ -995,37 +1218,6 @@ CONFIG.DIN_FROM {3} \ CONFIG.DOUT_WIDTH {4} \ ] $xlslice_1 - # Create instance: xlslice_2, and set properties - set xlslice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_2 ] - set_property -dict [ list \ -CONFIG.DIN_FROM {15} \ -CONFIG.DOUT_WIDTH {16} \ - ] $xlslice_2 - - # Create instance: xlslice_3, and set properties - set xlslice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_3 ] - set_property -dict [ list \ -CONFIG.DIN_FROM {19} \ -CONFIG.DIN_TO {4} \ -CONFIG.DOUT_WIDTH {16} \ - ] $xlslice_3 - - # Create instance: xlslice_4, and set properties - set xlslice_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_4 ] - set_property -dict [ list \ -CONFIG.DIN_FROM {20} \ -CONFIG.DIN_TO {20} \ -CONFIG.DOUT_WIDTH {1} \ - ] $xlslice_4 - - # Create instance: xlslice_5, and set properties - set xlslice_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_5 ] - set_property -dict [ list \ -CONFIG.DIN_FROM {21} \ -CONFIG.DIN_TO {21} \ -CONFIG.DOUT_WIDTH {1} \ - ] $xlslice_5 - # Create instance: zero_16, and set properties set zero_16 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 zero_16 ] set_property -dict [ list \ @@ -1034,98 +1226,134 @@ CONFIG.CONST_WIDTH {16} \ ] $zero_16 # Create interface connections - connect_bd_intf_net -intf_net AXI_StreamCapture_0_m_axis_s2mm [get_bd_intf_pins AXI_StreamCapture_0/m_axis_s2mm] [get_bd_intf_pins axi_datamover_0/S_AXIS_S2MM] - connect_bd_intf_net -intf_net AXI_StreamCapture_0_m_axis_s2mm_cmd [get_bd_intf_pins AXI_StreamCapture_0/m_axis_s2mm_cmd] [get_bd_intf_pins axi_datamover_0/S_AXIS_S2MM_CMD] - connect_bd_intf_net -intf_net Angle_RPM_Ib_Ia_m_axis [get_bd_intf_pins Angle_RPM_Ib_Ia/m_axis] [get_bd_intf_pins rx_fifo/S_AXIS] -connect_bd_intf_net -intf_net [get_bd_intf_nets Angle_RPM_Ib_Ia_m_axis] [get_bd_intf_pins axis_monitor_1/s00_axis] [get_bd_intf_pins rx_fifo/S_AXIS] -connect_bd_intf_net -intf_net Conn [get_bd_intf_pins FOC/s_axis_V1] [get_bd_intf_pins axis_monitor_1/s01_axis] -connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins FOC/SLOT_0_AXIS] [get_bd_intf_pins axis_monitor_1/s02_axis] -connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins FOC/m_axis] [get_bd_intf_pins axis_monitor_1/s03_axis] -connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins FOC/s_axis_V2] [get_bd_intf_pins axis_monitor_1/s04_axis] -connect_bd_intf_net -intf_net Conn4 [get_bd_intf_pins FOC/SLOT_0_AXIS1] [get_bd_intf_pins axis_monitor_1/s05_axis] - connect_bd_intf_net -intf_net FOC_m_axis_V [get_bd_intf_pins FOC/m_axis_V] [get_bd_intf_pins tx_fifo/S_AXIS] -connect_bd_intf_net -intf_net [get_bd_intf_nets FOC_m_axis_V] [get_bd_intf_pins axis_monitor_1/s06_axis] [get_bd_intf_pins tx_fifo/S_AXIS] - connect_bd_intf_net -intf_net axi_datamover_0_M_AXIS_S2MM_STS [get_bd_intf_pins AXI_StreamCapture_0/s_axis_s2mm_sts] [get_bd_intf_pins axi_datamover_0/M_AXIS_S2MM_STS] + connect_bd_intf_net -intf_net AXI_StreamCapture_0_m_axis_s2mm [get_bd_intf_pins axi_datamover_0/S_AXIS_S2MM] [get_bd_intf_pins capture_axi_PYNQ/m_axis_s2mm] + connect_bd_intf_net -intf_net AXI_StreamCapture_0_m_axis_s2mm_cmd [get_bd_intf_pins axi_datamover_0/S_AXIS_S2MM_CMD] [get_bd_intf_pins capture_axi_PYNQ/m_axis_s2mm_cmd] + connect_bd_intf_net -intf_net Angle_RPM_Ib_Ia_m_axis [get_bd_intf_pins Angle_RPM_Ib_Ia/m_axis] [get_bd_intf_pins FOC/I_ab_raw] +connect_bd_intf_net -intf_net Conn [get_bd_intf_pins FOC/I_ab_raw_m] [get_bd_intf_pins axis_monitor_0/s01_axis] +connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins FOC/I_alphabeta_m] [get_bd_intf_pins axis_monitor_0/s02_axis] +connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins FCSMPC/Idq_m] [get_bd_intf_pins FOC/I_dq_m] +connect_bd_intf_net -intf_net [get_bd_intf_nets Conn2] [get_bd_intf_pins FOC/I_dq_m] [get_bd_intf_pins axis_monitor_0/s03_axis] +connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins FOC/V_dq_m] [get_bd_intf_pins axis_monitor_0/s04_axis] +connect_bd_intf_net -intf_net Conn4 [get_bd_intf_pins FOC/V_PWM_m] [get_bd_intf_pins axis_monitor_0/s07_axis] +connect_bd_intf_net -intf_net Conn5 [get_bd_intf_pins FOC/V_abc_m] [get_bd_intf_pins axis_monitor_0/s06_axis] +connect_bd_intf_net -intf_net Conn6 [get_bd_intf_pins FOC/I_ab_Filtered_m] [get_bd_intf_pins axis_monitor_0/s00_axis] +connect_bd_intf_net -intf_net Conn7 [get_bd_intf_pins FOC/V_alphabeta_m] [get_bd_intf_pins axis_monitor_0/s05_axis] +connect_bd_intf_net -intf_net Conn9 [get_bd_intf_pins FCSMPC/ap_ctrl] [get_bd_intf_pins system_ila_0/SLOT_3_ACC_HANDSHAKE] + connect_bd_intf_net -intf_net FOC_m_axis_V [get_bd_intf_pins FOC/V_PWM] [get_bd_intf_pins axis_pwm_0/S_AXIS] + connect_bd_intf_net -intf_net axi_datamover_0_M_AXIS_S2MM_STS [get_bd_intf_pins axi_datamover_0/M_AXIS_S2MM_STS] [get_bd_intf_pins capture_axi_PYNQ/s_axis_s2mm_sts] connect_bd_intf_net -intf_net axi_datamover_0_M_AXI_S2MM [get_bd_intf_pins axi_datamover_0/M_AXI_S2MM] [get_bd_intf_pins axi_interconnect_0/S00_AXI] connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_pins axi_interconnect_0/M00_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP0] connect_bd_intf_net -intf_net axis_AD7403_0_m_axis [get_bd_intf_pins axis_AD7403_0/m_axis] [get_bd_intf_pins axis_data_fifo_1/S_AXIS] - connect_bd_intf_net -intf_net axis_data_fifo_0_M_AXIS [get_bd_intf_pins AXI_StreamCapture_0/s_axis] [get_bd_intf_pins axis_data_fifo_0/M_AXIS] - connect_bd_intf_net -intf_net axis_data_fifo_1_M_AXIS [get_bd_intf_pins Ib_Ia/S_AXIS] [get_bd_intf_pins axis_data_fifo_1/M_AXIS] - connect_bd_intf_net -intf_net axis_decimate_0_m_axis [get_bd_intf_pins axis_data_fifo_0/S_AXIS] [get_bd_intf_pins axis_decimate_0/m_axis] +connect_bd_intf_net -intf_net [get_bd_intf_nets axis_AD7403_0_m_axis] [get_bd_intf_pins axis_data_fifo_1/S_AXIS] [get_bd_intf_pins system_ila_0/SLOT_1_AXIS] + set_property -dict [ list \ +HDL_ATTRIBUTE.DEBUG {true} \ + ] [get_bd_intf_nets axis_AD7403_0_m_axis] + connect_bd_intf_net -intf_net axis_data_fifo_0_M_AXIS [get_bd_intf_pins Decimate_Samples/m_axis] [get_bd_intf_pins axis_data_fifo_0/S_AXIS] + connect_bd_intf_net -intf_net axis_data_fifo_0_M_AXIS1 [get_bd_intf_pins axis_data_fifo_0/M_AXIS] [get_bd_intf_pins capture_axi_PYNQ/s_axis] + connect_bd_intf_net -intf_net axis_data_fifo_1_M_AXIS [get_bd_intf_pins I_a_Ib/S_AXIS] [get_bd_intf_pins axis_data_fifo_1/M_AXIS] connect_bd_intf_net -intf_net axis_encoder_0_m_angle [get_bd_intf_pins Angle_RPM_Ib_Ia/sc_axis] [get_bd_intf_pins axis_encoder_0/m_angle] connect_bd_intf_net -intf_net axis_encoder_0_m_rpm [get_bd_intf_pins Angle_RPM_Ib_Ia/sb_axis] [get_bd_intf_pins axis_encoder_0/m_rpm] - connect_bd_intf_net -intf_net axis_monitor_1_m_axis [get_bd_intf_pins axis_decimate_0/s_axis] [get_bd_intf_pins axis_monitor_1/m_axis] - connect_bd_intf_net -intf_net axis_subset_converter_0_M_AXIS [get_bd_intf_pins Angle_RPM_Ib_Ia/sa_axis] [get_bd_intf_pins Ib_Ia/M_AXIS] + connect_bd_intf_net -intf_net axis_monitor_0_m_axis [get_bd_intf_pins Decimate_Samples/s_axis] [get_bd_intf_pins axis_monitor_0/m_axis] +connect_bd_intf_net -intf_net [get_bd_intf_nets axis_monitor_0_m_axis] [get_bd_intf_pins axis_monitor_0/m_axis] [get_bd_intf_pins system_ila_0/SLOT_0_AXIS] + set_property -dict [ list \ +HDL_ATTRIBUTE.DEBUG {true} \ + ] [get_bd_intf_nets axis_monitor_0_m_axis] + connect_bd_intf_net -intf_net axis_subset_converter_0_M_AXIS [get_bd_intf_pins Angle_RPM_Ib_Ia/sa_axis] [get_bd_intf_pins I_a_Ib/M_AXIS] connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR] connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO] connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins ps7_0_axi_periph/S00_AXI] - connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI [get_bd_intf_pins axi_reg32_0/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M00_AXI] - connect_bd_intf_net -intf_net ps7_0_axi_periph_M01_AXI [get_bd_intf_pins AXI_StreamCapture_0/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M01_AXI] - connect_bd_intf_net -intf_net rx_fifo_M_AXIS [get_bd_intf_pins FOC/s_axis_V] [get_bd_intf_pins rx_fifo/M_AXIS] - connect_bd_intf_net -intf_net tx_fifo_M_AXIS [get_bd_intf_pins axis_pwm_0/S_AXIS] [get_bd_intf_pins tx_fifo/M_AXIS] + connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI [get_bd_intf_pins control_axi_block/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M00_AXI] + connect_bd_intf_net -intf_net ps7_0_axi_periph_M01_AXI [get_bd_intf_pins capture_axi_PYNQ/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M01_AXI] # Create port connections - connect_bd_net -net A_1 [get_bd_ports ENC_A] [get_bd_pins axis_encoder_0/A] + connect_bd_net -net ARESETN_1 [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins ps7_0_axi_periph/ARESETN] + connect_bd_net -net A_1 [get_bd_ports ENC_A] [get_bd_pins axis_encoder_0/A] [get_bd_pins xlconcat_2/In2] connect_bd_net -net Angle_Shift_slice_Dout [get_bd_pins Angle_Shift_slice/Dout] [get_bd_pins axis_encoder_0/angle_shift] - connect_bd_net -net BTN0_1 [get_bd_ports BTN0] [get_bd_pins rpm_check_0/button] - connect_bd_net -net B_1 [get_bd_ports ENC_B] [get_bd_pins axis_encoder_0/B] - connect_bd_net -net FOC_Id_out [get_bd_pins FOC/Id_out] [get_bd_pins axi_reg32_0/RR2] - connect_bd_net -net FOC_Iq_out [get_bd_pins FOC/Iq_out] [get_bd_pins axi_reg32_0/RR3] - connect_bd_net -net FOC_dout [get_bd_pins FOC/RPM] [get_bd_pins axi_reg32_0/RR1] [get_bd_pins xlslice_2/Din] - connect_bd_net -net I_1 [get_bd_ports ENC_I] [get_bd_pins axis_encoder_0/I] + connect_bd_net -net B_1 [get_bd_ports ENC_B] [get_bd_pins axis_encoder_0/B] [get_bd_pins xlconcat_2/In3] + connect_bd_net -net FCSMPC_GH [get_bd_pins FCSMPC/GH] [get_bd_pins my_2_3MUX_0/B1] + connect_bd_net -net FCSMPC_GH_V_ap_vld [get_bd_pins FCSMPC/GH_V_ap_vld] [get_bd_pins system_ila_0/probe2] + connect_bd_net -net FCSMPC_GL [get_bd_pins FCSMPC/GL] [get_bd_pins my_2_3MUX_0/A1] + connect_bd_net -net FCSMPC_Id_exp [get_bd_pins FCSMPC/Id_exp] [get_bd_pins system_ila_0/probe3] + connect_bd_net -net FCSMPC_Id_out [get_bd_pins FCSMPC/Id_out] [get_bd_pins system_ila_0/probe0] + connect_bd_net -net FCSMPC_Iq_exp [get_bd_pins FCSMPC/Iq_exp] [get_bd_pins system_ila_0/probe4] + connect_bd_net -net FCSMPC_Iq_out [get_bd_pins FCSMPC/Iq_out] [get_bd_pins system_ila_0/probe1] + connect_bd_net -net FOC_Id_out [get_bd_pins FOC/Id_out] [get_bd_pins control_axi_block/RR2] + connect_bd_net -net FOC_Iq_out [get_bd_pins FOC/Iq_out] [get_bd_pins control_axi_block/RR3] + connect_bd_net -net FOC_dout [get_bd_pins FOC/RPM] [get_bd_pins control_axi_block/RR1] + connect_bd_net -net I_1 [get_bd_ports ENC_I] [get_bd_pins axis_encoder_0/I] [get_bd_pins xlconcat_2/In1] connect_bd_net -net SDI1_1 [get_bd_ports SDI1] [get_bd_pins xlconcat_0/In0] connect_bd_net -net SDI2_1 [get_bd_ports SDI2] [get_bd_pins xlconcat_0/In1] connect_bd_net -net SDI3_1 [get_bd_ports SDI3] [get_bd_pins xlconcat_0/In2] connect_bd_net -net SDV_1 [get_bd_ports SDV] [get_bd_pins xlconcat_0/In3] - connect_bd_net -net SW0_1 [get_bd_ports SW0] [get_bd_pins clk_mux_0/sel] [get_bd_pins rpm_check_0/ss_in] - connect_bd_net -net Vq_1 [get_bd_pins FOC/Vq] [get_bd_pins axi_reg32_0/WR12] - connect_bd_net -net axi_reg32_0_WR0 [get_bd_pins FOC/control] [get_bd_pins axi_reg32_0/WR0] [get_bd_pins rpm_check_0/mode_in] - connect_bd_net -net axi_reg32_0_WR1 [get_bd_pins FOC/Flux_Sp] [get_bd_pins axi_reg32_0/WR1] - connect_bd_net -net axi_reg32_0_WR2 [get_bd_pins FOC/Flux_Kp] [get_bd_pins axi_reg32_0/WR2] - connect_bd_net -net axi_reg32_0_WR3 [get_bd_pins FOC/Flux_Ki] [get_bd_pins axi_reg32_0/WR3] - connect_bd_net -net axi_reg32_0_WR4 [get_bd_pins FOC/Torque_Sp] [get_bd_pins axi_reg32_0/WR4] - connect_bd_net -net axi_reg32_0_WR5 [get_bd_pins FOC/Torque_Kp] [get_bd_pins axi_reg32_0/WR5] - connect_bd_net -net axi_reg32_0_WR6 [get_bd_pins FOC/Torque_Ki] [get_bd_pins axi_reg32_0/WR6] - connect_bd_net -net axi_reg32_0_WR7 [get_bd_pins FOC/RPM_Sp] [get_bd_pins axi_reg32_0/WR7] - connect_bd_net -net axi_reg32_0_WR8 [get_bd_pins FOC/RPM_Kp] [get_bd_pins axi_reg32_0/WR8] - connect_bd_net -net axi_reg32_0_WR9 [get_bd_pins FOC/RPM_Ki] [get_bd_pins axi_reg32_0/WR9] - connect_bd_net -net axi_reg32_0_WR10 [get_bd_pins Angle_Shift_slice/Din] [get_bd_pins axi_reg32_0/WR10] - connect_bd_net -net axi_reg32_0_WR11 [get_bd_pins FOC/Vd] [get_bd_pins axi_reg32_0/WR11] - connect_bd_net -net axi_reg32_0_WR13 [get_bd_pins axi_reg32_0/WR13] [get_bd_pins axis_decimate_0/decimation] - connect_bd_net -net axi_reg32_0_WR14 [get_bd_pins axi_reg32_0/WR14] [get_bd_pins xlslice_0/Din] - connect_bd_net -net axi_reg32_0_WR15 [get_bd_pins axi_reg32_0/WR15] [get_bd_pins xlslice_1/Din] [get_bd_pins xlslice_3/Din] [get_bd_pins xlslice_4/Din] [get_bd_pins xlslice_5/Din] + connect_bd_net -net SW_0_1 [get_bd_ports SW_0] [get_bd_pins my_2_3MUX_0/SEL] [get_bd_pins system_ila_0/probe7] [get_bd_pins xlconcat_2/In0] + connect_bd_net -net Vq_1 [get_bd_pins FOC/Vq] [get_bd_pins control_axi_block/WR12] + connect_bd_net -net axi_reg32_0_WR0 [get_bd_pins FOC/control] [get_bd_pins control_axi_block/WR0] + connect_bd_net -net axi_reg32_0_WR1 [get_bd_pins FOC/Flux_Sp] [get_bd_pins control_axi_block/WR1] + connect_bd_net -net axi_reg32_0_WR2 [get_bd_pins FOC/Flux_Kp] [get_bd_pins control_axi_block/WR2] + connect_bd_net -net axi_reg32_0_WR3 [get_bd_pins FOC/Flux_Ki] [get_bd_pins control_axi_block/WR3] + connect_bd_net -net axi_reg32_0_WR4 [get_bd_pins FCSMPC/iq_SP] [get_bd_pins FOC/Torque_Sp] [get_bd_pins control_axi_block/WR4] + connect_bd_net -net axi_reg32_0_WR5 [get_bd_pins FOC/Torque_Kp] [get_bd_pins control_axi_block/WR5] + connect_bd_net -net axi_reg32_0_WR6 [get_bd_pins FOC/Torque_Ki] [get_bd_pins control_axi_block/WR6] + connect_bd_net -net axi_reg32_0_WR7 [get_bd_pins FOC/RPM_Sp] [get_bd_pins control_axi_block/WR7] + connect_bd_net -net axi_reg32_0_WR8 [get_bd_pins FOC/RPM_Kp] [get_bd_pins control_axi_block/WR8] + connect_bd_net -net axi_reg32_0_WR9 [get_bd_pins FOC/RPM_Ki] [get_bd_pins control_axi_block/WR9] + connect_bd_net -net axi_reg32_0_WR10 [get_bd_pins Angle_Shift_slice/Din] [get_bd_pins control_axi_block/WR10] + connect_bd_net -net axi_reg32_0_WR11 [get_bd_pins FOC/Vd] [get_bd_pins control_axi_block/WR11] + connect_bd_net -net axi_reg32_0_WR13 [get_bd_pins Decimate_Samples/decimation] [get_bd_pins control_axi_block/WR13] connect_bd_net -net axis_AD7403_0_clkout [get_bd_ports SCLK] [get_bd_pins axis_AD7403_0/clkout] - connect_bd_net -net axis_encoder_0_angle_data [get_bd_pins Angle_concat/In0] [get_bd_pins axis_encoder_0/angle_data] - connect_bd_net -net axis_pwm_0_pwm_h [get_bd_ports GH] [get_bd_pins axis_pwm_0/pwm_h] - connect_bd_net -net axis_pwm_0_pwm_l [get_bd_ports GL] [get_bd_pins axis_pwm_0/pwm_l] - connect_bd_net -net clk_mux_0_clkout [get_bd_pins axis_AD7403_0/m_axis_aclk] [get_bd_pins axis_data_fifo_1/s_axis_aclk] [get_bd_pins clk_mux_0/clkout] [get_bd_pins proc_sys_reset_1/slowest_sync_clk] - connect_bd_net -net clk_wiz_0_clk_out1 [get_bd_pins clk_mux_0/clk1] [get_bd_pins clk_wiz_0/clk_out1] - connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins ps7_0_axi_periph/ARESETN] - connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins AXI_StreamCapture_0/axi_aresetn] [get_bd_pins Angle_RPM_Ib_Ia/s_axis_aresetn] [get_bd_pins FOC/ap_rst_n] [get_bd_pins Ib_Ia/aresetn] [get_bd_pins axi_datamover_0/m_axi_s2mm_aresetn] [get_bd_pins axi_datamover_0/m_axis_s2mm_cmdsts_aresetn] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_reg32_0/s_axi_aresetn] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins axis_data_fifo_1/m_axis_aresetn] [get_bd_pins axis_decimate_0/s_axis_aresetn] [get_bd_pins axis_encoder_0/axis_aresetn] [get_bd_pins axis_monitor_1/axis_aresetn] [get_bd_pins axis_pwm_0/s_axis_aresetn] [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/M01_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins rx_fifo/s_axis_aresetn] [get_bd_pins tx_fifo/s_axis_aresetn] - connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axis_AD7403_0/m_axis_aresetn] [get_bd_pins axis_data_fifo_1/s_axis_aresetn] [get_bd_pins proc_sys_reset_1/peripheral_aresetn] - connect_bd_net -net processing_system7_0_FCLK_CLK1 [get_bd_pins AXI_StreamCapture_0/axi_aclk] [get_bd_pins Angle_RPM_Ib_Ia/s_axis_aclk] [get_bd_pins FOC/ap_clk] [get_bd_pins Ib_Ia/aclk] [get_bd_pins axi_datamover_0/m_axi_s2mm_aclk] [get_bd_pins axi_datamover_0/m_axis_s2mm_cmdsts_awclk] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins axi_reg32_0/s_axi_aclk] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins axis_data_fifo_1/m_axis_aclk] [get_bd_pins axis_decimate_0/s_axis_aclk] [get_bd_pins axis_encoder_0/axis_aclk] [get_bd_pins axis_monitor_1/axis_aclk] [get_bd_pins axis_pwm_0/s_axis_aclk] [get_bd_pins clk_mux_0/clk0] [get_bd_pins clk_wiz_0/clk_in1] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/M01_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins rpm_check_0/aclk] [get_bd_pins rx_fifo/s_axis_aclk] [get_bd_pins tx_fifo/s_axis_aclk] - connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins proc_sys_reset_0/ext_reset_in] [get_bd_pins proc_sys_reset_1/ext_reset_in] [get_bd_pins processing_system7_0/FCLK_RESET0_N] - connect_bd_net -net rpm_check_0_led [get_bd_ports led] [get_bd_pins rpm_check_0/led] [get_bd_pins xlconcat_1/In0] + connect_bd_net -net axis_encoder_0_angle_data [get_bd_pins Angle_concat/In0] [get_bd_pins FCSMPC/angle] [get_bd_pins axis_encoder_0/angle_data] + connect_bd_net -net axis_pwm_0_pwm_h [get_bd_pins axis_pwm_0/pwm_h] [get_bd_pins my_2_3MUX_0/B0] + connect_bd_net -net axis_pwm_0_pwm_l [get_bd_pins axis_pwm_0/pwm_l] [get_bd_pins my_2_3MUX_0/A0] + connect_bd_net -net control_axi_block_WR14 [get_bd_pins FCSMPC/MPC_Control] [get_bd_pins control_axi_block/WR14] + connect_bd_net -net control_axi_block_WR15 [get_bd_pins control_axi_block/WR15] [get_bd_pins xlslice_1/Din] + connect_bd_net -net fit_timer_0_Interrupt [get_bd_pins fit_timer_0/Interrupt] [get_bd_pins system_ila_0/probe5] + connect_bd_net -net my_2_3MUX_0_A [get_bd_ports GL] [get_bd_pins my_2_3MUX_0/A] [get_bd_pins system_ila_0/probe6] + set_property -dict [ list \ +HDL_ATTRIBUTE.DEBUG {true} \ + ] [get_bd_nets my_2_3MUX_0_A] + connect_bd_net -net my_2_3MUX_0_B [get_bd_ports GH] [get_bd_pins my_2_3MUX_0/B] + connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins Angle_RPM_Ib_Ia/s_axis_aresetn] [get_bd_pins Decimate_Samples/s_axis_aresetn] [get_bd_pins FCSMPC/axis_in_aresetn] [get_bd_pins FOC/ap_rst_n] [get_bd_pins I_a_Ib/aresetn] [get_bd_pins axi_datamover_0/m_axi_s2mm_aresetn] [get_bd_pins axi_datamover_0/m_axis_s2mm_cmdsts_aresetn] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axis_AD7403_0/m_axis_aresetn] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins axis_data_fifo_1/s_axis_aresetn] [get_bd_pins axis_encoder_0/axis_aresetn] [get_bd_pins axis_monitor_0/axis_aresetn] [get_bd_pins axis_pwm_0/s_axis_aresetn] [get_bd_pins capture_axi_PYNQ/axi_aresetn] [get_bd_pins control_axi_block/s_axi_aresetn] [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/M01_ARESETN] [get_bd_pins ps7_0_axi_periph/M02_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins system_ila_0/resetn] + connect_bd_net -net proc_sys_reset_0_peripheral_reset [get_bd_pins fit_timer_0/Rst] [get_bd_pins proc_sys_reset_0/peripheral_reset] + connect_bd_net -net processing_system7_0_FCLK_CLK1 [get_bd_pins Angle_RPM_Ib_Ia/s_axis_aclk] [get_bd_pins Decimate_Samples/s_axis_aclk] [get_bd_pins FCSMPC/ap_clk] [get_bd_pins FOC/ap_clk] [get_bd_pins I_a_Ib/aclk] [get_bd_pins Phase_Test_0/CLK] [get_bd_pins axi_datamover_0/m_axi_s2mm_aclk] [get_bd_pins axi_datamover_0/m_axis_s2mm_cmdsts_awclk] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins axis_AD7403_0/m_axis_aclk] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins axis_data_fifo_1/s_axis_aclk] [get_bd_pins axis_encoder_0/axis_aclk] [get_bd_pins axis_monitor_0/axis_aclk] [get_bd_pins axis_pwm_0/s_axis_aclk] [get_bd_pins capture_axi_PYNQ/axi_aclk] [get_bd_pins control_axi_block/s_axi_aclk] [get_bd_pins fit_timer_0/Clk] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/M01_ACLK] [get_bd_pins ps7_0_axi_periph/M02_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins system_ila_0/clk] + connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins proc_sys_reset_0/ext_reset_in] [get_bd_pins processing_system7_0/FCLK_RESET0_N] connect_bd_net -net xlconcat_0_dout [get_bd_pins axis_AD7403_0/din] [get_bd_pins xlconcat_0/dout] - connect_bd_net -net xlconcat_1_dout [get_bd_pins Angle_concat/dout] [get_bd_pins axi_reg32_0/RR0] - connect_bd_net -net xlconcat_1_dout1 [get_bd_pins axi_reg32_0/RR4] [get_bd_pins xlconcat_1/dout] - connect_bd_net -net xlconstant_0_dout [get_bd_pins xlconcat_1/In1] [get_bd_pins xlconstant_0/dout] - connect_bd_net -net xlslice_1_Dout [get_bd_pins axis_monitor_1/mux_in] [get_bd_pins xlslice_1/Dout] - connect_bd_net -net xlslice_2_Dout [get_bd_pins rpm_check_0/rpm_data] [get_bd_pins xlslice_2/Dout] - connect_bd_net -net xlslice_3_Dout [get_bd_pins rpm_check_0/tolerance_in] [get_bd_pins xlslice_3/Dout] - connect_bd_net -net xlslice_4_Dout [get_bd_pins rpm_check_0/led_in] [get_bd_pins xlslice_4/Dout] - connect_bd_net -net xlslice_5_Dout [get_bd_pins rpm_check_0/restart_in] [get_bd_pins xlslice_5/Dout] + connect_bd_net -net xlconcat_1_dout [get_bd_pins Angle_concat/dout] [get_bd_pins control_axi_block/RR0] + connect_bd_net -net xlconcat_2_dout [get_bd_ports led] [get_bd_pins xlconcat_2/dout] + connect_bd_net -net xlslice_1_Dout [get_bd_pins axis_monitor_0/mux_in] [get_bd_pins xlslice_1/Dout] connect_bd_net -net zero_16_dout [get_bd_pins Angle_concat/In1] [get_bd_pins zero_16/dout] # Create address segments create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces axi_datamover_0/Data_S2MM] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_HP0_DDR_LOWOCM - create_bd_addr_seg -range 0x00010000 -offset 0x43C10000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs AXI_StreamCapture_0/S_AXI/S_AXI_reg] SEG_AXI_StreamCapture_0_S_AXI_reg - create_bd_addr_seg -range 0x00010000 -offset 0x43C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_reg32_0/S_AXI/S_AXI_reg] SEG_axi_reg32_0_S_AXI_reg + create_bd_addr_seg -range 0x00010000 -offset 0x43C10000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs capture_axi_PYNQ/S_AXI/S_AXI_reg] SEG_AXI_StreamCapture_0_S_AXI_reg + create_bd_addr_seg -range 0x00010000 -offset 0x43C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs control_axi_block/S_AXI/S_AXI_reg] SEG_axi_reg32_0_S_AXI_reg # Restore current instance current_bd_instance $oldCurInst + # Add USER_COMMENTS on $design_name + variable design_name + set_property USER_COMMENTS.comment_1 "0 Control +1 Flux_SP +2 Flux_KP +3 Flux_KI +4 Torq_SP +5 Torq_KP +6 Torq_KI +7 RPM_SP +8 RPM_KP +9 RPM_KI +10 Shift +11 VD +12 VQ +13 Decimate +14 MPC Control +15 Corntrol2" [get_bd_designs $design_name] + set_property USER_COMMENTS.comment_2 "0 Angle +1 Speed +2 I_d +3 I_q +4 debug" [get_bd_designs $design_name] save_bd_design } # End of create_root_design() diff --git a/boards/Arty-Z7-10/spyn/vivado/constraints/Arty_Z7.xdc b/boards/Arty-Z7-10/spyn/vivado/constraints/Arty_Z7.xdc deleted file mode 100644 index 6af9edb..0000000 --- a/boards/Arty-Z7-10/spyn/vivado/constraints/Arty_Z7.xdc +++ /dev/null @@ -1,54 +0,0 @@ -#set_property PACKAGE_PIN W15 [get_ports { shield_spi_io0_io }]; #IO_L10N_T1_34 Sch=ck_miso -#set_property PACKAGE_PIN T12 [get_ports { shield_spi_io1_io }]; #IO_L2P_T0_34 Sch=ck_mosi -#set_property PACKAGE_PIN H15 [get_ports { shield_spi_sck_io }]; #IO_L19P_T3_35 Sch=ck_sck -#set_property PACKAGE_PIN P16 [get_ports { shield_iic_scl_io }]; #IO_L24N_T3_34 Sch=ck_scl -#set_property PACKAGE_PIN P15 [get_ports { shield_iic_sda_io }]; #IO_L24P_T3_34 Sch=ck_sda -#set_property PACKAGE_PIN F16 [get_ports { shield_spi_ss_io }]; #IO_L6P_T0_35 Sch=ck_ss - - -#set_property PACKAGE_PIN W19 [get_ports {gpio_0_tri_io[0]}]; # EXT1 -#set_property IOSTANDARD LVCMOS33 [get_ports gpio_0_tri_io[0]] -# J9 <-> PMODA -set_property PACKAGE_PIN Y18 [get_ports {SCLK}]; # J9:1 SCLK -> PMODA:1 JA1_P -set_property PACKAGE_PIN Y19 [get_ports {SDI1}]; # J9:2 SDI1 -> PMODA:2 JA1_N -set_property PACKAGE_PIN Y16 [get_ports {SDI2}]; # J9:3 SDI2 -> PMODA:3 JA2_P -set_property PACKAGE_PIN Y17 [get_ports {SDI3}]; # J9:4 SDI3 -> PMODA:4 JA2_N -set_property PACKAGE_PIN U18 [get_ports {SDV}]; # J9:7 SDV -> PMODA:7 JA3_P -set_property PACKAGE_PIN U19 [get_ports {ENC_A}]; # J9:8 ENC_A -> PMODA:8 JA3_N -set_property PACKAGE_PIN W18 [get_ports {ENC_B}]; # J9:9 ENC_B -> PMODA:9 JA4_P -set_property PACKAGE_PIN W19 [get_ports {ENC_I}]; # J9:10 ENC_I -> PMODA:10 JA4_N -set_property IOSTANDARD LVCMOS33 [get_ports SCLK] -set_property IOSTANDARD LVCMOS33 [get_ports SDI*] -set_property IOSTANDARD LVCMOS33 [get_ports SDV] -set_property IOSTANDARD LVCMOS33 [get_ports ENC_*] -# J8 <-> PMODB -set_property PACKAGE_PIN W14 [get_ports {GH[0]}]; # J8:1 G1H -> PMODB:1 JB1_P -set_property PACKAGE_PIN Y14 [get_ports {GH[1]}]; # J8:2 G2H -> PMODB:1 JB1_N -set_property PACKAGE_PIN T11 [get_ports {GH[2]}]; # J8:3 G3H -> PMODB:1 JB2_P -#set_property PACKAGE_PIN T10 [get_ports {gpio_0_tri_io[1]}]; # J8:4 EXT2 -> PMODB:1 JB2_N -set_property PACKAGE_PIN V16 [get_ports {GL[0]}]; # J8:7 G1L -> PMODB:1 JB3_P -set_property PACKAGE_PIN W16 [get_ports {GL[1]}]; # J8:8 G2L -> PMODB:1 JB3_N -set_property PACKAGE_PIN V12 [get_ports {GL[2]}]; # J8:9 G3L -> PMODB:1 JB4_P -#set_property PACKAGE_PIN W13 [get_ports {gpio_0_tri_io[0]}]; # J8:10 EXT1 -> PMODB:1 JB4_N -#set_property IOSTANDARD LVCMOS33 [get_ports gpio_0_tri_io*] -set_property IOSTANDARD LVCMOS33 [get_ports GH*] -set_property IOSTANDARD LVCMOS33 [get_ports GL*] -set_property DRIVE 4 [get_ports GL*] -set_property DRIVE 4 [get_ports GH*] -set_property DRIVE 4 [get_ports SCLK] -set_property SLEW SLOW [get_ports SCLK] -set_property SLEW SLOW [get_ports GL*] -set_property SLEW SLOW [get_ports GH*] - -set_property PACKAGE_PIN R14 [get_ports {led[0]}] -set_property PACKAGE_PIN P14 [get_ports {led[1]}] -set_property PACKAGE_PIN N16 [get_ports {led[2]}] -set_property PACKAGE_PIN M14 [get_ports {led[3]}] -set_property IOSTANDARD LVCMOS33 [get_ports led*] -set_property PACKAGE_PIN D19 [get_ports BTN0] -#set_property PACKAGE_PIN D20 [get_ports BTN1] -#set_property PACKAGE_PIN L20 [get_ports BTN2] -#set_property PACKAGE_PIN L19 [get_ports BTN3] -set_property IOSTANDARD LVCMOS33 [get_ports BTN*] -set_property PACKAGE_PIN M20 [get_ports SW0] -set_property IOSTANDARD LVCMOS33 [get_ports SW*] \ No newline at end of file diff --git a/boards/Arty-Z7-10/spyn/vivado/zsys_wrapper.vhd b/boards/Arty-Z7-10/spyn/vivado/zsys_wrapper.vhd deleted file mode 100644 index c309895..0000000 --- a/boards/Arty-Z7-10/spyn/vivado/zsys_wrapper.vhd +++ /dev/null @@ -1,130 +0,0 @@ ---Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. ----------------------------------------------------------------------------------- ---Tool Version: Vivado v.2017.1_sdx (win64) Build 1915620 Thu Jun 22 17:54:58 MDT 2017 ---Date : Fri Apr 26 13:54:16 2019 ---Host : TUEIEAL-TS09 running 64-bit major release (build 9200) ---Command : generate_target zsys_wrapper.bd ---Design : zsys_wrapper ---Purpose : IP block netlist ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -library UNISIM; -use UNISIM.VCOMPONENTS.ALL; -entity zsys_wrapper is - port ( - BTN0 : in STD_LOGIC; - DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); - DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 ); - DDR_cas_n : inout STD_LOGIC; - DDR_ck_n : inout STD_LOGIC; - DDR_ck_p : inout STD_LOGIC; - DDR_cke : inout STD_LOGIC; - DDR_cs_n : inout STD_LOGIC; - DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 ); - DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 ); - DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); - DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 ); - DDR_odt : inout STD_LOGIC; - DDR_ras_n : inout STD_LOGIC; - DDR_reset_n : inout STD_LOGIC; - DDR_we_n : inout STD_LOGIC; - ENC_A : in STD_LOGIC; - ENC_B : in STD_LOGIC; - ENC_I : in STD_LOGIC; - FIXED_IO_ddr_vrn : inout STD_LOGIC; - FIXED_IO_ddr_vrp : inout STD_LOGIC; - FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 ); - FIXED_IO_ps_clk : inout STD_LOGIC; - FIXED_IO_ps_porb : inout STD_LOGIC; - FIXED_IO_ps_srstb : inout STD_LOGIC; - GH : out STD_LOGIC_VECTOR ( 2 downto 0 ); - GL : out STD_LOGIC_VECTOR ( 2 downto 0 ); - SCLK : out STD_LOGIC; - SDI1 : in STD_LOGIC; - SDI2 : in STD_LOGIC; - SDI3 : in STD_LOGIC; - SDV : in STD_LOGIC; - SW0 : in STD_LOGIC; - led : out STD_LOGIC_VECTOR ( 3 downto 0 ) - ); -end zsys_wrapper; - -architecture STRUCTURE of zsys_wrapper is - component zsys is - port ( - DDR_cas_n : inout STD_LOGIC; - DDR_cke : inout STD_LOGIC; - DDR_ck_n : inout STD_LOGIC; - DDR_ck_p : inout STD_LOGIC; - DDR_cs_n : inout STD_LOGIC; - DDR_reset_n : inout STD_LOGIC; - DDR_odt : inout STD_LOGIC; - DDR_ras_n : inout STD_LOGIC; - DDR_we_n : inout STD_LOGIC; - DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 ); - DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); - DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 ); - DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 ); - DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); - DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 ); - FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 ); - FIXED_IO_ddr_vrn : inout STD_LOGIC; - FIXED_IO_ddr_vrp : inout STD_LOGIC; - FIXED_IO_ps_srstb : inout STD_LOGIC; - FIXED_IO_ps_clk : inout STD_LOGIC; - FIXED_IO_ps_porb : inout STD_LOGIC; - ENC_A : in STD_LOGIC; - BTN0 : in STD_LOGIC; - ENC_B : in STD_LOGIC; - ENC_I : in STD_LOGIC; - SDI1 : in STD_LOGIC; - SDI2 : in STD_LOGIC; - SDI3 : in STD_LOGIC; - SDV : in STD_LOGIC; - SW0 : in STD_LOGIC; - SCLK : out STD_LOGIC; - GH : out STD_LOGIC_VECTOR ( 2 downto 0 ); - GL : out STD_LOGIC_VECTOR ( 2 downto 0 ); - led : out STD_LOGIC_VECTOR ( 3 downto 0 ) - ); - end component zsys; -begin -zsys_i: component zsys - port map ( - BTN0 => BTN0, - DDR_addr(14 downto 0) => DDR_addr(14 downto 0), - DDR_ba(2 downto 0) => DDR_ba(2 downto 0), - DDR_cas_n => DDR_cas_n, - DDR_ck_n => DDR_ck_n, - DDR_ck_p => DDR_ck_p, - DDR_cke => DDR_cke, - DDR_cs_n => DDR_cs_n, - DDR_dm(3 downto 0) => DDR_dm(3 downto 0), - DDR_dq(31 downto 0) => DDR_dq(31 downto 0), - DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0), - DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0), - DDR_odt => DDR_odt, - DDR_ras_n => DDR_ras_n, - DDR_reset_n => DDR_reset_n, - DDR_we_n => DDR_we_n, - ENC_A => ENC_A, - ENC_B => ENC_B, - ENC_I => ENC_I, - FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn, - FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp, - FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0), - FIXED_IO_ps_clk => FIXED_IO_ps_clk, - FIXED_IO_ps_porb => FIXED_IO_ps_porb, - FIXED_IO_ps_srstb => FIXED_IO_ps_srstb, - GH(2 downto 0) => GH(2 downto 0), - GL(2 downto 0) => GL(2 downto 0), - SCLK => SCLK, - SDI1 => SDI1, - SDI2 => SDI2, - SDI3 => SDI3, - SDV => SDV, - SW0 => SW0, - led(3 downto 0) => led(3 downto 0) - ); -end STRUCTURE; diff --git a/boards/Pynq-Z1/__init__.py b/boards/Pynq-Z1/__init__.py deleted file mode 100644 index 00c9436..0000000 --- a/boards/Pynq-Z1/__init__.py +++ /dev/null @@ -1,35 +0,0 @@ -# Copyright (c) 2018, Xilinx, Inc. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# 1. Redistributions of source code must retain the above copyright notice, -# this list of conditions and the following disclaimer. -# -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# -# 3. Neither the name of the copyright holder nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR -# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; -# OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR -# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - - -__author__ = "KV Thanjavur Bhaaskar, Naveen Purushotham" -__copyright__ = "Copyright 2018, Xilinx" -__email__ = "kvt@xilinx.com, npurusho@xilinx.com" - -from .spyn import SpynOverlay diff --git a/boards/Pynq-Z1/spyn.bit b/boards/Pynq-Z1/spyn.bit index 800edc0..4c6934a 100644 Binary files a/boards/Pynq-Z1/spyn.bit and b/boards/Pynq-Z1/spyn.bit differ diff --git a/boards/Pynq-Z1/spyn.hwh b/boards/Pynq-Z1/spyn.hwh index 57dd90c..b0d5b76 100644 --- a/boards/Pynq-Z1/spyn.hwh +++ b/boards/Pynq-Z1/spyn.hwh @@ -1,5 +1,5 @@  - + @@ -25,24 +25,23 @@ + - - - - - + + + @@ -65,30 +64,31 @@ - + - - + - + - + - + - + - + - + + + - + - + @@ -141,290 +141,112 @@ - + - - - - - - - - - - - + + + + + + + - - - + - + - - - - - - - - - - - - - - - - - - - - - - - - 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- + - + - + - + - + - + - - - - - - - - - - - - - + - + - - - - - - - - - - - - - - - + - + - @@ -8542,110 +12199,14 @@ - + - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + diff --git a/boards/Pynq-Z1/spyn.tcl b/boards/Pynq-Z1/spyn.tcl index 5178685..dac4dfe 100644 --- a/boards/Pynq-Z1/spyn.tcl +++ b/boards/Pynq-Z1/spyn.tcl @@ -1,1140 +1,88 @@ - -################################################################ -# This is a generated script based on design: zsys -# -# Though there are limitations about the generated script, -# the main purpose of this utility is to make learning -# IP Integrator Tcl commands easier. -################################################################ - -namespace eval _tcl { -proc get_script_folder {} { - set script_path [file normalize [info script]] - set script_folder [file dirname $script_path] - return $script_folder -} -} -variable script_folder -set script_folder [_tcl::get_script_folder] - -################################################################ -# Check if script is running in correct Vivado version. -################################################################ -set scripts_vivado_version 2017.1 -set current_vivado_version [version -short] - -if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { - puts "" - catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} - - return 1 -} - -################################################################ -# START -################################################################ - -# To test this script, run the following commands from Vivado Tcl console: -# source zsys_script.tcl - -# If there is no project opened, this script will create a -# project, but make sure you do not have an existing project -# <./myproj/project_1.xpr> in the current working folder. - -set list_projs [get_projects -quiet] -if { $list_projs eq "" } { - create_project project_1 myproj -part xc7z020clg400-1 - set_property BOARD_PART www.digilentinc.com:pynq-z1:part0:1.0 [current_project] -} - - -# CHANGE DESIGN NAME HERE -set design_name zsys - -# If you do not already have an existing IP Integrator design open, -# you can create a design using the following command: -# create_bd_design $design_name - -# Creating design if needed -set errMsg "" -set nRet 0 - -set cur_design [current_bd_design -quiet] -set list_cells [get_bd_cells -quiet] - -if { ${design_name} eq "" } { - # USE CASES: - # 1) Design_name not set - - set errMsg "Please set the variable to a non-empty value." - set nRet 1 - -} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { - # USE CASES: - # 2): Current design opened AND is empty AND names same. - # 3): Current design opened AND is empty AND names diff; design_name NOT in project. - # 4): Current design opened AND is empty AND names diff; design_name exists in project. - - if { $cur_design ne $design_name } { - common::send_msg_id "BD_TCL-001" "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." - set design_name [get_property NAME $cur_design] - } - common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." - -} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { - # USE CASES: - # 5) Current design opened AND has components AND same names. - - set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." - set nRet 1 -} elseif { [get_files -quiet ${design_name}.bd] ne "" } { - # USE CASES: - # 6) Current opened design, has components, but diff names, design_name exists in project. - # 7) No opened design, design_name exists in project. - - set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." - set nRet 2 - -} else { - # USE CASES: - # 8) No opened design, design_name not in project. - # 9) Current opened design, has components, but diff names, design_name not in project. - - common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." - - create_bd_design $design_name - - common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." - current_bd_design $design_name - +# +# Synthesis run script generated by Vivado +# + +set_param tcl.collectionResultDisplayLimit 0 +set_param xicom.use_bs_reader 1 +create_project -in_memory -part xc7z020clg400-1 + +set_param project.singleFileAddWarning.threshold 0 +set_param project.compositeFile.enableAutoGeneration 0 +set_param synth.vivado.isSynthRun true +set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info +set_property webtalk.parent_dir C:/Users/ga53xem/IIoT-EDDP/myWS/VivadoProjects/my_FOC/my_FOC.cache/wt [current_project] +set_property parent.project_path C:/Users/ga53xem/IIoT-EDDP/myWS/VivadoProjects/my_FOC/my_FOC.xpr [current_project] +set_property XPM_LIBRARIES {XPM_CDC XPM_MEMORY} [current_project] +set_property default_lib xil_defaultlib [current_project] +set_property target_language VHDL [current_project] +set_property board_part www.digilentinc.com:pynq-z1:part0:1.0 [current_project] +set_property ip_repo_paths { + c:/Users/ga53xem/IIoT-EDDP/myWS/VivadoProjects/Test/Ips/MPC_Trigger + c:/Users/ga53xem/IIoT-EDDP/myWS/VivadoProjects/ip_repo/AXI_to_Signal16_1.0 + c:/Users/ga53xem/IIoT-EDDP/myWS/VivadoProjects/ip_repo/AXI_to_Signal_1.0 + c:/Users/ga53xem/IIoT-EDDP/HLS/ARTY_Z7_FULL/ip_lib + c:/Users/ga53xem/FCSMPC_2.0/solution2 + c:/Users/ga53xem/P_Controller/solution2 +} [current_project] +set_property ip_output_repo c:/Users/ga53xem/IIoT-EDDP/myWS/VivadoProjects/my_FOC/my_FOC.cache/ip [current_project] +set_property ip_cache_permissions {read write} [current_project] +read_vhdl -library xil_defaultlib C:/Users/ga53xem/IIoT-EDDP/myWS/VivadoProjects/my_FOC/my_FOC.srcs/sources_1/bd/zsys/hdl/zsys_wrapper.vhd +add_files C:/Users/ga53xem/IIoT-EDDP/myWS/VivadoProjects/my_FOC/my_FOC.srcs/sources_1/bd/zsys/zsys.bd +set_property used_in_implementation false [get_files -all c:/Users/ga53xem/IIoT-EDDP/myWS/VivadoProjects/my_FOC/my_FOC.srcs/sources_1/bd/zsys/ip/zsys_axi_datamover_0_0/zsys_axi_datamover_0_0_ooc.xdc] +set_property used_in_implementation false [get_files -all c:/Users/ga53xem/IIoT-EDDP/myWS/VivadoProjects/my_FOC/my_FOC.srcs/sources_1/bd/zsys/ip/zsys_axi_datamover_0_0/zsys_axi_datamover_0_0.xdc] +set_property used_in_implementation false [get_files -all c:/Users/ga53xem/IIoT-EDDP/myWS/VivadoProjects/my_FOC/my_FOC.srcs/sources_1/bd/zsys/ip/zsys_axi_datamover_0_0/zsys_axi_datamover_0_0_clocks.xdc] +set_property used_in_implementation false [get_files -all c:/Users/ga53xem/IIoT-EDDP/myWS/VivadoProjects/my_FOC/my_FOC.srcs/sources_1/bd/zsys/ip/zsys_proc_sys_reset_0_0/zsys_proc_sys_reset_0_0_board.xdc] +set_property used_in_implementation false [get_files -all c:/Users/ga53xem/IIoT-EDDP/myWS/VivadoProjects/my_FOC/my_FOC.srcs/sources_1/bd/zsys/ip/zsys_proc_sys_reset_0_0/zsys_proc_sys_reset_0_0.xdc] +set_property used_in_implementation false [get_files -all c:/Users/ga53xem/IIoT-EDDP/myWS/VivadoProjects/my_FOC/my_FOC.srcs/sources_1/bd/zsys/ip/zsys_proc_sys_reset_0_0/zsys_proc_sys_reset_0_0_ooc.xdc] +set_property used_in_implementation false [get_files -all c:/Users/ga53xem/IIoT-EDDP/myWS/VivadoProjects/my_FOC/my_FOC.srcs/sources_1/bd/zsys/ip/zsys_processing_system7_0_0/zsys_processing_system7_0_0.xdc] +set_property used_in_implementation false [get_files -all c:/Users/ga53xem/IIoT-EDDP/myWS/VivadoProjects/my_FOC/my_FOC.srcs/sources_1/bd/zsys/ip/zsys_Clarke_Direct_0_0/constraints/Clarke_Direct_ooc.xdc] +set_property used_in_implementation false [get_files -all c:/Users/ga53xem/IIoT-EDDP/myWS/VivadoProjects/my_FOC/my_FOC.srcs/sources_1/bd/zsys/ip/zsys_Clarke_Inverse_0_0/constraints/Clarke_Inverse_ooc.xdc] +set_property used_in_implementation false [get_files -all c:/Users/ga53xem/IIoT-EDDP/myWS/VivadoProjects/my_FOC/my_FOC.srcs/sources_1/bd/zsys/ip/zsys_Filters_0_0/constraints/Filters_ooc.xdc] +set_property used_in_implementation false [get_files -all c:/Users/ga53xem/IIoT-EDDP/myWS/VivadoProjects/my_FOC/my_FOC.srcs/sources_1/bd/zsys/ip/zsys_Flux_PI_Control_0/constraints/PI_Control_ooc.xdc] +set_property used_in_implementation false [get_files -all c:/Users/ga53xem/IIoT-EDDP/myWS/VivadoProjects/my_FOC/my_FOC.srcs/sources_1/bd/zsys/ip/zsys_Park_Direct_0_0/constraints/Park_Direct_ooc.xdc] +set_property used_in_implementation false [get_files -all c:/Users/ga53xem/IIoT-EDDP/myWS/VivadoProjects/my_FOC/my_FOC.srcs/sources_1/bd/zsys/ip/zsys_Park_Inverse_0_0/constraints/Park_Inverse_ooc.xdc] +set_property used_in_implementation false [get_files -all c:/Users/ga53xem/IIoT-EDDP/myWS/VivadoProjects/my_FOC/my_FOC.srcs/sources_1/bd/zsys/ip/zsys_RPM_PI_Control_0/constraints/PI_Control_ooc.xdc] +set_property used_in_implementation false [get_files -all c:/Users/ga53xem/IIoT-EDDP/myWS/VivadoProjects/my_FOC/my_FOC.srcs/sources_1/bd/zsys/ip/zsys_SVPWM_0_0/constraints/SVPWM_ooc.xdc] +set_property used_in_implementation false [get_files -all c:/Users/ga53xem/IIoT-EDDP/myWS/VivadoProjects/my_FOC/my_FOC.srcs/sources_1/bd/zsys/ip/zsys_Torque_PI_Control_0/constraints/PI_Control_ooc.xdc] +set_property used_in_implementation false [get_files -all c:/Users/ga53xem/IIoT-EDDP/myWS/VivadoProjects/my_FOC/my_FOC.srcs/sources_1/bd/zsys/ip/zsys_axis_broadcaster_0_0/zsys_axis_broadcaster_0_0_ooc.xdc] +set_property used_in_implementation false [get_files -all c:/Users/ga53xem/IIoT-EDDP/myWS/VivadoProjects/my_FOC/my_FOC.srcs/sources_1/bd/zsys/ip/zsys_axis_data_fifo_0_0/zsys_axis_data_fifo_0_0_ooc.xdc] +set_property used_in_implementation false [get_files -all c:/Users/ga53xem/IIoT-EDDP/myWS/VivadoProjects/my_FOC/my_FOC.srcs/sources_1/bd/zsys/ip/zsys_axis_data_fifo_0_0/zsys_axis_data_fifo_0_0/zsys_axis_data_fifo_0_0.xdc] +set_property used_in_implementation false [get_files -all c:/Users/ga53xem/IIoT-EDDP/myWS/VivadoProjects/my_FOC/my_FOC.srcs/sources_1/bd/zsys/ip/zsys_axis_subset_converter_0_0/zsys_axis_subset_converter_0_0_ooc.xdc] +set_property used_in_implementation false [get_files -all c:/Users/ga53xem/IIoT-EDDP/myWS/VivadoProjects/my_FOC/my_FOC.srcs/sources_1/bd/zsys/ip/zsys_axis_data_fifo_1_2/zsys_axis_data_fifo_1_2_ooc.xdc] +set_property used_in_implementation false [get_files -all c:/Users/ga53xem/IIoT-EDDP/myWS/VivadoProjects/my_FOC/my_FOC.srcs/sources_1/bd/zsys/ip/zsys_axis_data_fifo_1_2/zsys_axis_data_fifo_1_2/zsys_axis_data_fifo_1_2.xdc] +set_property used_in_implementation false [get_files -all c:/Users/ga53xem/IIoT-EDDP/myWS/VivadoProjects/my_FOC/my_FOC.srcs/sources_1/bd/zsys/ip/zsys_FCSMPC_0_1/constraints/FCSMPC_ooc.xdc] +set_property used_in_implementation false [get_files -all c:/Users/ga53xem/IIoT-EDDP/myWS/VivadoProjects/my_FOC/my_FOC.srcs/sources_1/bd/zsys/ip/zsys_xbar_0/zsys_xbar_0_ooc.xdc] +set_property used_in_implementation false [get_files -all c:/Users/ga53xem/IIoT-EDDP/myWS/VivadoProjects/my_FOC/my_FOC.srcs/sources_1/bd/zsys/ip/zsys_fit_timer_0_0/zsys_fit_timer_0_0_ooc.xdc] +set_property used_in_implementation false [get_files -all c:/Users/ga53xem/IIoT-EDDP/myWS/VivadoProjects/my_FOC/my_FOC.srcs/sources_1/bd/zsys/ip/zsys_system_ila_0_1/bd_1/ip/ip_0/ila_v6_2/constraints/ila.xdc] +set_property used_in_implementation false [get_files -all c:/Users/ga53xem/IIoT-EDDP/myWS/VivadoProjects/my_FOC/my_FOC.srcs/sources_1/bd/zsys/ip/zsys_system_ila_0_1/bd_1/ip/ip_0/bd_3489_ila_lib_0_ooc.xdc] +set_property used_in_implementation false [get_files -all c:/Users/ga53xem/IIoT-EDDP/myWS/VivadoProjects/my_FOC/my_FOC.srcs/sources_1/bd/zsys/ip/zsys_system_ila_0_1/bd_1/bd_3489_ooc.xdc] +set_property used_in_implementation false [get_files -all c:/Users/ga53xem/IIoT-EDDP/myWS/VivadoProjects/my_FOC/my_FOC.srcs/sources_1/bd/zsys/ip/zsys_auto_pc_2/zsys_auto_pc_2_ooc.xdc] +set_property used_in_implementation false [get_files -all c:/Users/ga53xem/IIoT-EDDP/myWS/VivadoProjects/my_FOC/my_FOC.srcs/sources_1/bd/zsys/ip/zsys_auto_pc_1/zsys_auto_pc_1_ooc.xdc] +set_property used_in_implementation false [get_files -all c:/Users/ga53xem/IIoT-EDDP/myWS/VivadoProjects/my_FOC/my_FOC.srcs/sources_1/bd/zsys/ip/zsys_auto_pc_3/zsys_auto_pc_3_ooc.xdc] +set_property used_in_implementation false [get_files -all c:/Users/ga53xem/IIoT-EDDP/myWS/VivadoProjects/my_FOC/my_FOC.srcs/sources_1/bd/zsys/ip/zsys_auto_pc_0/zsys_auto_pc_0_ooc.xdc] +set_property used_in_implementation false [get_files -all C:/Users/ga53xem/IIoT-EDDP/myWS/VivadoProjects/my_FOC/my_FOC.srcs/sources_1/bd/zsys/zsys_ooc.xdc] +set_property is_locked true [get_files C:/Users/ga53xem/IIoT-EDDP/myWS/VivadoProjects/my_FOC/my_FOC.srcs/sources_1/bd/zsys/zsys.bd] + +# Mark all dcp files as not used in implementation to prevent them from being +# stitched into the results of this synthesis run. Any black boxes in the +# design are intentionally left as such for best results. Dcp files will be +# stitched into the design at a later time, either when this synthesis run is +# opened, or when it is stitched into a dependent implementation run. +foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] { + set_property used_in_implementation false $dcp } +read_xdc C:/Users/ga53xem/IIoT-EDDP/myWS/VivadoProjects/my_FOC/my_FOC.srcs/constrs_1/imports/constraints/Arty_Z7.xdc +set_property used_in_implementation false [get_files C:/Users/ga53xem/IIoT-EDDP/myWS/VivadoProjects/my_FOC/my_FOC.srcs/constrs_1/imports/constraints/Arty_Z7.xdc] -common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable is equal to \"$design_name\"." - -if { $nRet != 0 } { - catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} - return $nRet -} - -################################################################## -# DESIGN PROCs -################################################################## - - -# Hierarchical cell: FOC -proc create_hier_cell_FOC { parentCell nameHier } { - - variable script_folder - - if { $parentCell eq "" || $nameHier eq "" } { - catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_FOC() - Empty argument(s)!"} - return - } - - # Get object for parentCell - set parentObj [get_bd_cells $parentCell] - if { $parentObj == "" } { - catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} - return - } - - # Make sure parentObj is hier blk - set parentType [get_property TYPE $parentObj] - if { $parentType ne "hier" } { - catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} - return - } - - # Save current instance; Restore later - set oldCurInst [current_bd_instance .] - - # Set parent object as current - current_bd_instance $parentObj - - # Create cell and set as current instance - set hier_obj [create_bd_cell -type hier $nameHier] - current_bd_instance $hier_obj - - # Create interface pins - create_bd_intf_pin -mode Monitor -vlnv xilinx.com:interface:axis_rtl:1.0 SLOT_0_AXIS - create_bd_intf_pin -mode Monitor -vlnv xilinx.com:interface:axis_rtl:1.0 SLOT_0_AXIS1 - create_bd_intf_pin -mode Monitor -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis - create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_V - create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_V - create_bd_intf_pin -mode Monitor -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_V1 - create_bd_intf_pin -mode Monitor -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_V2 - - # Create pins - create_bd_pin -dir I -from 31 -to 0 Flux_Ki - create_bd_pin -dir I -from 31 -to 0 Flux_Kp - create_bd_pin -dir I -from 31 -to 0 Flux_Sp - create_bd_pin -dir O -from 31 -to 0 -type data Id_out - create_bd_pin -dir O -from 31 -to 0 -type data Iq_out - create_bd_pin -dir O -from 31 -to 0 RPM - create_bd_pin -dir I -from 31 -to 0 RPM_Ki - create_bd_pin -dir I -from 31 -to 0 RPM_Kp - create_bd_pin -dir I -from 31 -to 0 RPM_Sp - create_bd_pin -dir I -from 31 -to 0 Torque_Ki - create_bd_pin -dir I -from 31 -to 0 Torque_Kp - create_bd_pin -dir I -from 31 -to 0 Torque_Sp - create_bd_pin -dir I -from 31 -to 0 Vd - create_bd_pin -dir I -from 31 -to 0 Vq - create_bd_pin -dir I -type clk ap_clk - create_bd_pin -dir I -type rst ap_rst_n - create_bd_pin -dir I -from 31 -to 0 -type data control - - # Create instance: Clarke_Direct_0, and set properties - set Clarke_Direct_0 [ create_bd_cell -type ip -vlnv trenz.biz:hls:Clarke_Direct:1.0 Clarke_Direct_0 ] - - # Create instance: Clarke_Inverse_0, and set properties - set Clarke_Inverse_0 [ create_bd_cell -type ip -vlnv trenz.biz:hls:Clarke_Inverse:1.0 Clarke_Inverse_0 ] - - # Create instance: Filters_0, and set properties - set Filters_0 [ create_bd_cell -type ip -vlnv trenz.biz:hls:Filters:1.0 Filters_0 ] - - # Create instance: Flux_Ki_slice, and set properties - set Flux_Ki_slice [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 Flux_Ki_slice ] - set_property -dict [ list \ -CONFIG.DIN_FROM {15} \ -CONFIG.DOUT_WIDTH {16} \ - ] $Flux_Ki_slice - - # Create instance: Flux_Kp_slice, and set properties - set Flux_Kp_slice [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 Flux_Kp_slice ] - set_property -dict [ list \ -CONFIG.DIN_FROM {15} \ -CONFIG.DOUT_WIDTH {16} \ - ] $Flux_Kp_slice - - # Create instance: Flux_PI_Control, and set properties - set Flux_PI_Control [ create_bd_cell -type ip -vlnv trenz.biz:hls:PI_Control:1.0 Flux_PI_Control ] - - # Create instance: Flux_Sp_slice, and set properties - set Flux_Sp_slice [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 Flux_Sp_slice ] - set_property -dict [ list \ -CONFIG.DIN_FROM {15} \ -CONFIG.DOUT_WIDTH {16} \ - ] $Flux_Sp_slice - - # Create instance: Park_Direct_0, and set properties - set Park_Direct_0 [ create_bd_cell -type ip -vlnv trenz.biz:hls:Park_Direct:1.0 Park_Direct_0 ] - - # Create instance: Park_Inverse_0, and set properties - set Park_Inverse_0 [ create_bd_cell -type ip -vlnv trenz.biz:hls:Park_Inverse:1.0 Park_Inverse_0 ] - - # Create instance: RPM_Ki_slice, and set properties - set RPM_Ki_slice [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 RPM_Ki_slice ] - set_property -dict [ list \ -CONFIG.DIN_FROM {15} \ -CONFIG.DOUT_WIDTH {16} \ - ] $RPM_Ki_slice - - # Create instance: RPM_Kp_slice, and set properties - set RPM_Kp_slice [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 RPM_Kp_slice ] - set_property -dict [ list \ -CONFIG.DIN_FROM {15} \ -CONFIG.DOUT_WIDTH {16} \ - ] $RPM_Kp_slice - - # Create instance: RPM_PI_Control, and set properties - set RPM_PI_Control [ create_bd_cell -type ip -vlnv trenz.biz:hls:PI_Control:1.0 RPM_PI_Control ] - - # Create instance: RPM_Sp_slice, and set properties - set RPM_Sp_slice [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 RPM_Sp_slice ] - set_property -dict [ list \ -CONFIG.DIN_FROM {15} \ -CONFIG.DOUT_WIDTH {16} \ - ] $RPM_Sp_slice - - # Create instance: SVPWM_0, and set properties - set SVPWM_0 [ create_bd_cell -type ip -vlnv trenz.biz:hls:SVPWM:1.0 SVPWM_0 ] - - # Create instance: Torque_Ki_slice, and set properties - set Torque_Ki_slice [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 Torque_Ki_slice ] - set_property -dict [ list \ -CONFIG.DIN_FROM {15} \ -CONFIG.DOUT_WIDTH {16} \ - ] $Torque_Ki_slice - - # Create instance: Torque_Kp_slice, and set properties - set Torque_Kp_slice [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 Torque_Kp_slice ] - set_property -dict [ list \ -CONFIG.DIN_FROM {15} \ -CONFIG.DOUT_WIDTH {16} \ - ] $Torque_Kp_slice - - # Create instance: Torque_PI_Control, and set properties - set Torque_PI_Control [ create_bd_cell -type ip -vlnv trenz.biz:hls:PI_Control:1.0 Torque_PI_Control ] - - # Create instance: Torque_Sp_slice, and set properties - set Torque_Sp_slice [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 Torque_Sp_slice ] - set_property -dict [ list \ -CONFIG.DIN_FROM {15} \ -CONFIG.DOUT_WIDTH {16} \ - ] $Torque_Sp_slice - - # Create instance: axis_broadcaster_0, and set properties - set axis_broadcaster_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_broadcaster:1.1 axis_broadcaster_0 ] - set_property -dict [ list \ -CONFIG.M00_TDATA_REMAP {tdata[15:0]} \ -CONFIG.M01_TDATA_REMAP {tdata[31:16]} \ -CONFIG.M02_TDATA_REMAP {tdata[47:32]} \ -CONFIG.M03_TDATA_REMAP {tdata[63:48]} \ -CONFIG.M_TDATA_NUM_BYTES {2} \ -CONFIG.NUM_MI {4} \ -CONFIG.S_TDATA_NUM_BYTES {8} \ - ] $axis_broadcaster_0 - - # Create instance: flux_limit, and set properties - set flux_limit [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 flux_limit ] - set_property -dict [ list \ -CONFIG.CONST_VAL {16777215} \ -CONFIG.CONST_WIDTH {32} \ - ] $flux_limit - - # Create instance: foc_control_0, and set properties - set foc_control_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:foc_control:1.0 foc_control_0 ] - - # Create instance: one, and set properties - set one [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 one ] - - # Create instance: rpm_limit, and set properties - set rpm_limit [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 rpm_limit ] - set_property -dict [ list \ -CONFIG.CONST_VAL {16777215} \ -CONFIG.CONST_WIDTH {32} \ - ] $rpm_limit - - # Create instance: torque_limit, and set properties - set torque_limit [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 torque_limit ] - set_property -dict [ list \ -CONFIG.CONST_VAL {16777215} \ -CONFIG.CONST_WIDTH {32} \ - ] $torque_limit - - # Create interface connections - connect_bd_intf_net -intf_net Clarke_Direct_0_m_axis_V [get_bd_intf_pins Clarke_Direct_0/m_axis_V] [get_bd_intf_pins Park_Direct_0/s_axis_V] - connect_bd_intf_net -intf_net [get_bd_intf_nets Clarke_Direct_0_m_axis_V] [get_bd_intf_pins s_axis_V1] [get_bd_intf_pins Clarke_Direct_0/m_axis_V] - connect_bd_intf_net -intf_net Clarke_Inverse_0_m_axis_V [get_bd_intf_pins Clarke_Inverse_0/m_axis_V] [get_bd_intf_pins SVPWM_0/s_axis_V] - connect_bd_intf_net -intf_net [get_bd_intf_nets Clarke_Inverse_0_m_axis_V] [get_bd_intf_pins SLOT_0_AXIS1] [get_bd_intf_pins Clarke_Inverse_0/m_axis_V] - connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins s_axis_V] [get_bd_intf_pins Filters_0/s_axis_V] - connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins m_axis_V] [get_bd_intf_pins SVPWM_0/m_axis_V] - connect_bd_intf_net -intf_net Filters_0_m_axis_V [get_bd_intf_pins Clarke_Direct_0/s_axis_V] [get_bd_intf_pins Filters_0/m_axis_V] - connect_bd_intf_net -intf_net Flux_PI_Control_m_axis_V [get_bd_intf_pins Flux_PI_Control/m_axis_V] [get_bd_intf_pins foc_control_0/s_flux] - connect_bd_intf_net -intf_net Park_Direct_0_m_axis_V [get_bd_intf_pins Park_Direct_0/m_axis_V] [get_bd_intf_pins axis_broadcaster_0/S_AXIS] - connect_bd_intf_net -intf_net [get_bd_intf_nets Park_Direct_0_m_axis_V] [get_bd_intf_pins SLOT_0_AXIS] [get_bd_intf_pins axis_broadcaster_0/S_AXIS] - connect_bd_intf_net -intf_net Park_Inverse_0_m_axis_V [get_bd_intf_pins Clarke_Inverse_0/s_axis_V] [get_bd_intf_pins Park_Inverse_0/m_axis_V] - connect_bd_intf_net -intf_net [get_bd_intf_nets Park_Inverse_0_m_axis_V] [get_bd_intf_pins s_axis_V2] [get_bd_intf_pins Park_Inverse_0/m_axis_V] - connect_bd_intf_net -intf_net RPM_PI_Control_m_axis_V [get_bd_intf_pins RPM_PI_Control/m_axis_V] [get_bd_intf_pins foc_control_0/s_rpm] - connect_bd_intf_net -intf_net Torque_PI_Control_m_axis_V [get_bd_intf_pins Torque_PI_Control/m_axis_V] [get_bd_intf_pins foc_control_0/s_torque] - connect_bd_intf_net -intf_net axis_broadcaster_0_M00_AXIS [get_bd_intf_pins Flux_PI_Control/s_axis_V] [get_bd_intf_pins axis_broadcaster_0/M00_AXIS] - connect_bd_intf_net -intf_net axis_broadcaster_0_M01_AXIS [get_bd_intf_pins Torque_PI_Control/s_axis_V] [get_bd_intf_pins axis_broadcaster_0/M01_AXIS] - connect_bd_intf_net -intf_net axis_broadcaster_0_M02_AXIS [get_bd_intf_pins RPM_PI_Control/s_axis_V] [get_bd_intf_pins axis_broadcaster_0/M02_AXIS] - connect_bd_intf_net -intf_net axis_broadcaster_0_M03_AXIS [get_bd_intf_pins axis_broadcaster_0/M03_AXIS] [get_bd_intf_pins foc_control_0/s_angle] - connect_bd_intf_net -intf_net foc_control_0_m_axis [get_bd_intf_pins Park_Inverse_0/s_axis_V] [get_bd_intf_pins foc_control_0/m_axis] - connect_bd_intf_net -intf_net [get_bd_intf_nets foc_control_0_m_axis] [get_bd_intf_pins m_axis] [get_bd_intf_pins foc_control_0/m_axis] - - # Create port connections - connect_bd_net -net Din1_1 [get_bd_pins RPM_Kp] [get_bd_pins RPM_Kp_slice/Din] - connect_bd_net -net Din2_1 [get_bd_pins RPM_Ki] [get_bd_pins RPM_Ki_slice/Din] - connect_bd_net -net Din3_1 [get_bd_pins Flux_Sp] [get_bd_pins Flux_Sp_slice/Din] - connect_bd_net -net Din4_1 [get_bd_pins Flux_Kp] [get_bd_pins Flux_Kp_slice/Din] - connect_bd_net -net Din5_1 [get_bd_pins Flux_Ki] [get_bd_pins Flux_Ki_slice/Din] - connect_bd_net -net Din6_1 [get_bd_pins Torque_Kp] [get_bd_pins Torque_Kp_slice/Din] - connect_bd_net -net Din7_1 [get_bd_pins Torque_Ki] [get_bd_pins Torque_Ki_slice/Din] - connect_bd_net -net Din_1 [get_bd_pins RPM_Sp] [get_bd_pins RPM_Sp_slice/Din] - connect_bd_net -net Filters_0_RPM_out [get_bd_pins RPM] [get_bd_pins Filters_0/RPM_out] - connect_bd_net -net Flux_Ki_slice_Dout [get_bd_pins Flux_Ki_slice/Dout] [get_bd_pins Flux_PI_Control/Ki] - connect_bd_net -net Flux_Kp_slice_Dout [get_bd_pins Flux_Kp_slice/Dout] [get_bd_pins Flux_PI_Control/Kp] - connect_bd_net -net Flux_Sp_slice_Dout [get_bd_pins Flux_PI_Control/Sp] [get_bd_pins Flux_Sp_slice/Dout] - connect_bd_net -net Park_Direct_0_Id_out [get_bd_pins Id_out] [get_bd_pins Park_Direct_0/Id_out] - connect_bd_net -net Park_Direct_0_Iq_out [get_bd_pins Iq_out] [get_bd_pins Park_Direct_0/Iq_out] - connect_bd_net -net RPM_Ki_slice_Dout [get_bd_pins RPM_Ki_slice/Dout] [get_bd_pins RPM_PI_Control/Ki] - connect_bd_net -net RPM_Kp_slice_Dout [get_bd_pins RPM_Kp_slice/Dout] [get_bd_pins RPM_PI_Control/Kp] - connect_bd_net -net RPM_Sp_slice_Dout [get_bd_pins RPM_PI_Control/Sp] [get_bd_pins RPM_Sp_slice/Dout] - connect_bd_net -net Torque_Ki_slice_Dout [get_bd_pins Torque_Ki_slice/Dout] [get_bd_pins Torque_PI_Control/Ki] - connect_bd_net -net Torque_Kp_slice_Dout [get_bd_pins Torque_Kp_slice/Dout] [get_bd_pins Torque_PI_Control/Kp] - connect_bd_net -net Torque_Sp_1 [get_bd_pins Torque_Sp] [get_bd_pins Torque_Sp_slice/Din] - connect_bd_net -net Torque_Sp_slice_Dout [get_bd_pins Torque_Sp_slice/Dout] [get_bd_pins foc_control_0/torque_sp_in] - connect_bd_net -net Vd_1 [get_bd_pins Vd] [get_bd_pins foc_control_0/vd_in] - connect_bd_net -net Vq_1 [get_bd_pins Vq] [get_bd_pins foc_control_0/vq_in] - connect_bd_net -net ap_clk_1 [get_bd_pins ap_clk] [get_bd_pins Clarke_Direct_0/ap_clk] [get_bd_pins Clarke_Inverse_0/ap_clk] [get_bd_pins Filters_0/ap_clk] [get_bd_pins Flux_PI_Control/ap_clk] [get_bd_pins Park_Direct_0/ap_clk] [get_bd_pins Park_Inverse_0/ap_clk] [get_bd_pins RPM_PI_Control/ap_clk] [get_bd_pins SVPWM_0/ap_clk] [get_bd_pins Torque_PI_Control/ap_clk] [get_bd_pins axis_broadcaster_0/aclk] [get_bd_pins foc_control_0/axis_aclk] - connect_bd_net -net ap_rst_n_1 [get_bd_pins ap_rst_n] [get_bd_pins Clarke_Direct_0/ap_rst_n] [get_bd_pins Clarke_Inverse_0/ap_rst_n] [get_bd_pins Filters_0/ap_rst_n] [get_bd_pins Flux_PI_Control/ap_rst_n] [get_bd_pins Park_Direct_0/ap_rst_n] [get_bd_pins Park_Inverse_0/ap_rst_n] [get_bd_pins RPM_PI_Control/ap_rst_n] [get_bd_pins SVPWM_0/ap_rst_n] [get_bd_pins Torque_PI_Control/ap_rst_n] [get_bd_pins axis_broadcaster_0/aresetn] [get_bd_pins foc_control_0/axis_aresetn] - connect_bd_net -net control_1 [get_bd_pins control] [get_bd_pins Filters_0/control] [get_bd_pins Flux_PI_Control/mode] [get_bd_pins RPM_PI_Control/mode] [get_bd_pins Torque_PI_Control/mode] [get_bd_pins foc_control_0/control_in] - connect_bd_net -net flux_limit_dout [get_bd_pins Flux_PI_Control/limit] [get_bd_pins flux_limit/dout] - connect_bd_net -net foc_control_0_torque_sp_out [get_bd_pins Torque_PI_Control/Sp] [get_bd_pins foc_control_0/torque_sp_out] - connect_bd_net -net one_dout [get_bd_pins Clarke_Direct_0/ap_start] [get_bd_pins Clarke_Inverse_0/ap_start] [get_bd_pins Filters_0/ap_start] [get_bd_pins Flux_PI_Control/ap_start] [get_bd_pins Park_Direct_0/ap_start] [get_bd_pins Park_Inverse_0/ap_start] [get_bd_pins RPM_PI_Control/ap_start] [get_bd_pins SVPWM_0/ap_start] [get_bd_pins Torque_PI_Control/ap_start] [get_bd_pins one/dout] - connect_bd_net -net rpm_limit_dout [get_bd_pins RPM_PI_Control/limit] [get_bd_pins rpm_limit/dout] - connect_bd_net -net torque_limit_dout [get_bd_pins Torque_PI_Control/limit] [get_bd_pins torque_limit/dout] - - # Restore current instance - current_bd_instance $oldCurInst -} - - -# Procedure to create entire design; Provide argument to make -# procedure reusable. If parentCell is "", will use root. -proc create_root_design { parentCell } { - - variable script_folder - - if { $parentCell eq "" } { - set parentCell [get_bd_cells /] - } - - # Get object for parentCell - set parentObj [get_bd_cells $parentCell] - if { $parentObj == "" } { - catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} - return - } - - # Make sure parentObj is hier blk - set parentType [get_property TYPE $parentObj] - if { $parentType ne "hier" } { - catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} - return - } - - # Save current instance; Restore later - set oldCurInst [current_bd_instance .] - - # Set parent object as current - current_bd_instance $parentObj - - - # Create interface ports - set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ] - set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ] - - # Create ports - set BTN0 [ create_bd_port -dir I BTN0 ] - set ENC_A [ create_bd_port -dir I ENC_A ] - set ENC_B [ create_bd_port -dir I ENC_B ] - set ENC_I [ create_bd_port -dir I ENC_I ] - set GH [ create_bd_port -dir O -from 2 -to 0 GH ] - set GL [ create_bd_port -dir O -from 2 -to 0 GL ] - set SCLK [ create_bd_port -dir O SCLK ] - set SDI1 [ create_bd_port -dir I SDI1 ] - set SDI2 [ create_bd_port -dir I SDI2 ] - set SDI3 [ create_bd_port -dir I SDI3 ] - set SDV [ create_bd_port -dir I SDV ] - set SW0 [ create_bd_port -dir I SW0 ] - set led [ create_bd_port -dir O -from 3 -to 0 led ] - - # Create instance: AXI_StreamCapture_0, and set properties - set AXI_StreamCapture_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:AXI_StreamCapture:1.0 AXI_StreamCapture_0 ] - - # Create instance: Angle_RPM_Ib_Ia, and set properties - set Angle_RPM_Ib_Ia [ create_bd_cell -type ip -vlnv trenz.biz:user:axis_concat:1.0 Angle_RPM_Ib_Ia ] - set_property -dict [ list \ -CONFIG.C_A_TDATA_WIDTH {32} \ -CONFIG.C_IN_CHANNELS {3} \ -CONFIG.M_TDATA_WIDTH {64} \ - ] $Angle_RPM_Ib_Ia - - # Create instance: Angle_Shift_slice, and set properties - set Angle_Shift_slice [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 Angle_Shift_slice ] - set_property -dict [ list \ -CONFIG.DIN_FROM {15} \ -CONFIG.DOUT_WIDTH {16} \ - ] $Angle_Shift_slice - - # Create instance: Angle_concat, and set properties - set Angle_concat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 Angle_concat ] - set_property -dict [ list \ -CONFIG.IN0_WIDTH {16} \ -CONFIG.IN1_WIDTH {16} \ - ] $Angle_concat - - # Create instance: FOC - create_hier_cell_FOC [current_bd_instance .] FOC - - # Create instance: Ib_Ia, and set properties - set Ib_Ia [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_subset_converter:1.1 Ib_Ia ] - set_property -dict [ list \ -CONFIG.M_TDATA_NUM_BYTES {4} \ -CONFIG.S_TDATA_NUM_BYTES {8} \ -CONFIG.TDATA_REMAP {tdata[31:0]} \ - ] $Ib_Ia - - # Create instance: axi_datamover_0, and set properties - set axi_datamover_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_datamover:5.1 axi_datamover_0 ] - set_property -dict [ list \ -CONFIG.c_enable_mm2s {0} \ -CONFIG.c_include_mm2s {Omit} \ -CONFIG.c_include_mm2s_stsfifo {false} \ -CONFIG.c_m_axi_s2mm_id_width {0} \ -CONFIG.c_mm2s_include_sf {false} \ -CONFIG.c_s2mm_btt_used {23} \ -CONFIG.c_s2mm_burst_size {8} \ -CONFIG.c_s2mm_include_sf {false} \ -CONFIG.c_s2mm_support_indet_btt {true} \ - ] $axi_datamover_0 - - # Create instance: axi_interconnect_0, and set properties - set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ] - set_property -dict [ list \ -CONFIG.NUM_MI {1} \ - ] $axi_interconnect_0 - - # Create instance: axi_reg32_0, and set properties - set axi_reg32_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:axi_reg32:1.0 axi_reg32_0 ] - set_property -dict [ list \ -CONFIG.C_NUM_RO_REG {5} \ -CONFIG.C_NUM_WR_REG {16} \ -CONFIG.C_WR0_ALIAS {Control} \ -CONFIG.C_WR10_ALIAS {Angle Shift} \ -CONFIG.C_WR10_DEFAULT {719} \ -CONFIG.C_WR11_ALIAS {Vd} \ -CONFIG.C_WR11_DEFAULT {-7424} \ -CONFIG.C_WR12_ALIAS {Vq} \ -CONFIG.C_WR12_DEFAULT {15000} \ -CONFIG.C_WR13_ALIAS {Decimation} \ -CONFIG.C_WR14_ALIAS {TR_Control} \ -CONFIG.C_WR1_ALIAS {Flux Sp} \ -CONFIG.C_WR2_ALIAS {Flux Kp} \ -CONFIG.C_WR2_DEFAULT {-45056} \ -CONFIG.C_WR3_ALIAS {Flux Ki} \ -CONFIG.C_WR4_ALIAS {Torque Sp} \ -CONFIG.C_WR4_DEFAULT {100} \ -CONFIG.C_WR5_ALIAS {Torque Kp} \ -CONFIG.C_WR5_DEFAULT {256} \ -CONFIG.C_WR6_ALIAS {Torque Ki} \ -CONFIG.C_WR7_ALIAS {RPM Sp} \ -CONFIG.C_WR7_DEFAULT {3000} \ -CONFIG.C_WR8_ALIAS {RPM Kp} \ -CONFIG.C_WR8_DEFAULT {744} \ -CONFIG.C_WR9_ALIAS {RPM Ki} \ -CONFIG.C_WR9_DEFAULT {9} \ - ] $axi_reg32_0 - - # Create instance: axis_AD7403_0, and set properties - set axis_AD7403_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:axis_AD7403:1.0 axis_AD7403_0 ] - set_property -dict [ list \ -CONFIG.C_CLOCK_RATIO {5} \ -CONFIG.C_DECIMATION {128} \ -CONFIG.C_SIGNED {true} \ - ] $axis_AD7403_0 - - # Create instance: axis_data_fifo_0, and set properties - set axis_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:1.1 axis_data_fifo_0 ] - set_property -dict [ list \ -CONFIG.FIFO_DEPTH {4096} \ - ] $axis_data_fifo_0 - - # Create instance: axis_data_fifo_1, and set properties - set axis_data_fifo_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:1.1 axis_data_fifo_1 ] - set_property -dict [ list \ -CONFIG.IS_ACLK_ASYNC {1} \ - ] $axis_data_fifo_1 - - # Create instance: axis_decimate_0, and set properties - set axis_decimate_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:axis_decimate:1.0 axis_decimate_0 ] - set_property -dict [ list \ -CONFIG.C_TDATA_WIDTH {64} \ - ] $axis_decimate_0 - - # Create instance: axis_encoder_0, and set properties - set axis_encoder_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:axis_encoder:1.0 axis_encoder_0 ] - set_property -dict [ list \ -CONFIG.C_ANGLE_AXIS {true} \ -CONFIG.C_CPR {1000} \ -CONFIG.C_RPM_AXIS {true} \ -CONFIG.C_USE_SHIFT {true} \ - ] $axis_encoder_0 - - # Create instance: axis_monitor_1, and set properties - set axis_monitor_1 [ create_bd_cell -type ip -vlnv trenz.biz:user:axis_monitor:1.1 axis_monitor_1 ] - set_property -dict [ list \ -CONFIG.C_SLAVE_IF {7} \ - ] $axis_monitor_1 - - # Create instance: axis_pwm_0, and set properties - set axis_pwm_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:axis_pwm:1.0 axis_pwm_0 ] - set_property -dict [ list \ -CONFIG.C_CHANNELS {3} \ -CONFIG.C_DEADTIME_SYCLES {50} \ -CONFIG.C_IN_TYPE {1} \ -CONFIG.C_S_AXIS_TDATA_WIDTH {64} \ - ] $axis_pwm_0 - - # Create instance: clk_mux_0, and set properties - set clk_mux_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:clk_mux:1.0 clk_mux_0 ] - - # Create instance: clk_wiz_0, and set properties - set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.4 clk_wiz_0 ] - set_property -dict [ list \ -CONFIG.CLKOUT1_JITTER {236.910} \ -CONFIG.CLKOUT1_PHASE_ERROR {732.678} \ -CONFIG.CLKOUT1_REQUESTED_DUTY_CYCLE {50.0} \ -CONFIG.MMCM_BANDWIDTH {LOW} \ -CONFIG.MMCM_CLKFBOUT_MULT_F {21.000} \ -CONFIG.MMCM_CLKOUT0_DIVIDE_F {7.000} \ -CONFIG.MMCM_DIVCLK_DIVIDE {3} \ -CONFIG.USE_LOCKED {false} \ -CONFIG.USE_RESET {false} \ -CONFIG.USE_SPREAD_SPECTRUM {true} \ - ] $clk_wiz_0 - - # Create instance: proc_sys_reset_0, and set properties - set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ] - - # Create instance: proc_sys_reset_1, and set properties - set proc_sys_reset_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_1 ] - - # Create instance: processing_system7_0, and set properties - set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ] - set_property -dict [ list \ -CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {650.000000} \ -CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.096154} \ -CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \ -CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \ -CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {20.000000} \ -CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \ -CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {50.000000} \ -CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {108.333336} \ -CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {108.333336} \ -CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {108.333336} \ -CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {108.333336} \ -CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {108.333336} \ -CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {108.333336} \ -CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \ -CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {108.333336} \ -CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {650} \ -CONFIG.PCW_ARMPLL_CTRL_FBDIV {26} \ -CONFIG.PCW_CLK0_FREQ {100000000} \ -CONFIG.PCW_CLK1_FREQ {20000000} \ -CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1300.000} \ -CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {50} \ -CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {52} \ -CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {2} \ -CONFIG.PCW_DDRPLL_CTRL_FBDIV {21} \ -CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1050.000} \ -CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \ -CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \ -CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \ -CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {8} \ -CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \ -CONFIG.PCW_ENET0_RESET_ENABLE {1} \ -CONFIG.PCW_ENET0_RESET_IO {MIO 9} \ -CONFIG.PCW_ENET_RESET_ENABLE {1} \ -CONFIG.PCW_ENET_RESET_SELECT {Share reset pin} \ -CONFIG.PCW_EN_CLK1_PORT {1} \ -CONFIG.PCW_EN_EMIO_GPIO {1} \ -CONFIG.PCW_EN_ENET0 {1} \ -CONFIG.PCW_EN_GPIO {1} \ -CONFIG.PCW_EN_QSPI {1} \ -CONFIG.PCW_EN_SDIO0 {1} \ -CONFIG.PCW_EN_UART0 {1} \ -CONFIG.PCW_EN_UART1 {1} \ -CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5} \ -CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {2} \ -CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {10} \ -CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {5} \ -CONFIG.PCW_FCLK_CLK1_BUF {TRUE} \ -CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \ -CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {20} \ -CONFIG.PCW_FPGA_FCLK1_ENABLE {1} \ -CONFIG.PCW_FTM_CTI_IN0 {} \ -CONFIG.PCW_FTM_CTI_IN2 {} \ -CONFIG.PCW_FTM_CTI_OUT0 {} \ -CONFIG.PCW_FTM_CTI_OUT2 {} \ -CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1} \ -CONFIG.PCW_GPIO_EMIO_GPIO_IO {2} \ -CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {2} \ -CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \ -CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \ -CONFIG.PCW_I2C_RESET_ENABLE {1} \ -CONFIG.PCW_IOPLL_CTRL_FBDIV {20} \ -CONFIG.PCW_IO_IO_PLL_FREQMHZ {1000.000} \ -CONFIG.PCW_MIO_0_DIRECTION {inout} \ -CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \ -CONFIG.PCW_MIO_0_PULLUP {enabled} \ -CONFIG.PCW_MIO_0_SLEW {slow} \ -CONFIG.PCW_MIO_10_DIRECTION {inout} \ -CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} \ -CONFIG.PCW_MIO_10_PULLUP {enabled} \ -CONFIG.PCW_MIO_10_SLEW {slow} \ -CONFIG.PCW_MIO_11_DIRECTION {inout} \ -CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V} \ -CONFIG.PCW_MIO_11_PULLUP {enabled} \ -CONFIG.PCW_MIO_11_SLEW {slow} \ -CONFIG.PCW_MIO_12_DIRECTION {inout} \ -CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V} \ -CONFIG.PCW_MIO_12_PULLUP {enabled} \ -CONFIG.PCW_MIO_12_SLEW {slow} \ -CONFIG.PCW_MIO_13_DIRECTION {inout} \ -CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V} \ -CONFIG.PCW_MIO_13_PULLUP {enabled} \ -CONFIG.PCW_MIO_13_SLEW {slow} \ -CONFIG.PCW_MIO_14_DIRECTION {in} \ -CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V} \ -CONFIG.PCW_MIO_14_PULLUP {enabled} \ -CONFIG.PCW_MIO_14_SLEW {slow} \ -CONFIG.PCW_MIO_15_DIRECTION {out} \ -CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} \ -CONFIG.PCW_MIO_15_PULLUP {enabled} \ -CONFIG.PCW_MIO_15_SLEW {slow} \ -CONFIG.PCW_MIO_16_DIRECTION {out} \ -CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_16_PULLUP {enabled} \ -CONFIG.PCW_MIO_16_SLEW {slow} \ -CONFIG.PCW_MIO_17_DIRECTION {out} \ -CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_17_PULLUP {enabled} \ -CONFIG.PCW_MIO_17_SLEW {slow} \ -CONFIG.PCW_MIO_18_DIRECTION {out} \ -CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_18_PULLUP {enabled} \ -CONFIG.PCW_MIO_18_SLEW {slow} \ -CONFIG.PCW_MIO_19_DIRECTION {out} \ -CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_19_PULLUP {enabled} \ -CONFIG.PCW_MIO_19_SLEW {slow} \ -CONFIG.PCW_MIO_1_DIRECTION {out} \ -CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \ -CONFIG.PCW_MIO_1_PULLUP {enabled} \ -CONFIG.PCW_MIO_1_SLEW {slow} \ -CONFIG.PCW_MIO_20_DIRECTION {out} \ -CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_20_PULLUP {enabled} \ -CONFIG.PCW_MIO_20_SLEW {slow} \ -CONFIG.PCW_MIO_21_DIRECTION {out} \ -CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_21_PULLUP {enabled} \ -CONFIG.PCW_MIO_21_SLEW {slow} \ -CONFIG.PCW_MIO_22_DIRECTION {in} \ -CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_22_PULLUP {enabled} \ -CONFIG.PCW_MIO_22_SLEW {slow} \ -CONFIG.PCW_MIO_23_DIRECTION {in} \ -CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_23_PULLUP {enabled} \ -CONFIG.PCW_MIO_23_SLEW {slow} \ -CONFIG.PCW_MIO_24_DIRECTION {in} \ -CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_24_PULLUP {enabled} \ -CONFIG.PCW_MIO_24_SLEW {slow} \ -CONFIG.PCW_MIO_25_DIRECTION {in} \ -CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_25_PULLUP {enabled} \ -CONFIG.PCW_MIO_25_SLEW {slow} \ -CONFIG.PCW_MIO_26_DIRECTION {in} \ -CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_26_PULLUP {enabled} \ -CONFIG.PCW_MIO_26_SLEW {slow} \ -CONFIG.PCW_MIO_27_DIRECTION {in} \ -CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_27_PULLUP {enabled} \ -CONFIG.PCW_MIO_27_SLEW {slow} \ -CONFIG.PCW_MIO_28_DIRECTION {inout} \ -CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_28_PULLUP {enabled} \ -CONFIG.PCW_MIO_28_SLEW {slow} \ -CONFIG.PCW_MIO_29_DIRECTION {inout} \ -CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_29_PULLUP {enabled} \ -CONFIG.PCW_MIO_29_SLEW {slow} \ -CONFIG.PCW_MIO_2_DIRECTION {inout} \ -CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \ -CONFIG.PCW_MIO_2_PULLUP {disabled} \ -CONFIG.PCW_MIO_2_SLEW {slow} \ -CONFIG.PCW_MIO_30_DIRECTION {inout} \ -CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_30_PULLUP {enabled} \ -CONFIG.PCW_MIO_30_SLEW {slow} \ -CONFIG.PCW_MIO_31_DIRECTION {inout} \ -CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_31_PULLUP {enabled} \ -CONFIG.PCW_MIO_31_SLEW {slow} \ -CONFIG.PCW_MIO_32_DIRECTION {inout} \ -CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_32_PULLUP {enabled} \ -CONFIG.PCW_MIO_32_SLEW {slow} \ -CONFIG.PCW_MIO_33_DIRECTION {inout} \ -CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_33_PULLUP {enabled} \ -CONFIG.PCW_MIO_33_SLEW {slow} \ -CONFIG.PCW_MIO_34_DIRECTION {inout} \ -CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_34_PULLUP {enabled} \ -CONFIG.PCW_MIO_34_SLEW {slow} \ -CONFIG.PCW_MIO_35_DIRECTION {inout} \ -CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_35_PULLUP {enabled} \ -CONFIG.PCW_MIO_35_SLEW {slow} \ -CONFIG.PCW_MIO_36_DIRECTION {inout} \ -CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_36_PULLUP {enabled} \ -CONFIG.PCW_MIO_36_SLEW {slow} \ -CONFIG.PCW_MIO_37_DIRECTION {inout} \ -CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_37_PULLUP {enabled} \ -CONFIG.PCW_MIO_37_SLEW {slow} \ -CONFIG.PCW_MIO_38_DIRECTION {inout} \ -CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_38_PULLUP {enabled} \ -CONFIG.PCW_MIO_38_SLEW {slow} \ -CONFIG.PCW_MIO_39_DIRECTION {inout} \ -CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_39_PULLUP {enabled} \ -CONFIG.PCW_MIO_39_SLEW {slow} \ -CONFIG.PCW_MIO_3_DIRECTION {inout} \ -CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \ -CONFIG.PCW_MIO_3_PULLUP {disabled} \ -CONFIG.PCW_MIO_3_SLEW {slow} \ -CONFIG.PCW_MIO_40_DIRECTION {inout} \ -CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_40_PULLUP {enabled} \ -CONFIG.PCW_MIO_40_SLEW {slow} \ -CONFIG.PCW_MIO_41_DIRECTION {inout} \ -CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_41_PULLUP {enabled} \ -CONFIG.PCW_MIO_41_SLEW {slow} \ -CONFIG.PCW_MIO_42_DIRECTION {inout} \ -CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_42_PULLUP {enabled} \ -CONFIG.PCW_MIO_42_SLEW {slow} \ -CONFIG.PCW_MIO_43_DIRECTION {inout} \ -CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_43_PULLUP {enabled} \ -CONFIG.PCW_MIO_43_SLEW {slow} \ -CONFIG.PCW_MIO_44_DIRECTION {inout} \ -CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_44_PULLUP {enabled} \ -CONFIG.PCW_MIO_44_SLEW {slow} \ -CONFIG.PCW_MIO_45_DIRECTION {inout} \ -CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_45_PULLUP {enabled} \ -CONFIG.PCW_MIO_45_SLEW {slow} \ -CONFIG.PCW_MIO_46_DIRECTION {inout} \ -CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_46_PULLUP {enabled} \ -CONFIG.PCW_MIO_46_SLEW {slow} \ -CONFIG.PCW_MIO_47_DIRECTION {in} \ -CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_47_PULLUP {enabled} \ -CONFIG.PCW_MIO_47_SLEW {slow} \ -CONFIG.PCW_MIO_48_DIRECTION {out} \ -CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_48_PULLUP {enabled} \ -CONFIG.PCW_MIO_48_SLEW {slow} \ -CONFIG.PCW_MIO_49_DIRECTION {in} \ -CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_49_PULLUP {enabled} \ -CONFIG.PCW_MIO_49_SLEW {slow} \ -CONFIG.PCW_MIO_4_DIRECTION {inout} \ -CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \ -CONFIG.PCW_MIO_4_PULLUP {disabled} \ -CONFIG.PCW_MIO_4_SLEW {slow} \ -CONFIG.PCW_MIO_50_DIRECTION {inout} \ -CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_50_PULLUP {enabled} \ -CONFIG.PCW_MIO_50_SLEW {slow} \ -CONFIG.PCW_MIO_51_DIRECTION {inout} \ -CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_51_PULLUP {enabled} \ -CONFIG.PCW_MIO_51_SLEW {slow} \ -CONFIG.PCW_MIO_52_DIRECTION {out} \ -CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_52_PULLUP {enabled} \ -CONFIG.PCW_MIO_52_SLEW {slow} \ -CONFIG.PCW_MIO_53_DIRECTION {inout} \ -CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_53_PULLUP {enabled} \ -CONFIG.PCW_MIO_53_SLEW {slow} \ -CONFIG.PCW_MIO_5_DIRECTION {inout} \ -CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \ -CONFIG.PCW_MIO_5_PULLUP {disabled} \ -CONFIG.PCW_MIO_5_SLEW {slow} \ -CONFIG.PCW_MIO_6_DIRECTION {out} \ -CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \ -CONFIG.PCW_MIO_6_PULLUP {disabled} \ -CONFIG.PCW_MIO_6_SLEW {slow} \ -CONFIG.PCW_MIO_7_DIRECTION {out} \ -CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V} \ -CONFIG.PCW_MIO_7_PULLUP {disabled} \ -CONFIG.PCW_MIO_7_SLEW {slow} \ -CONFIG.PCW_MIO_8_DIRECTION {out} \ -CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V} \ -CONFIG.PCW_MIO_8_PULLUP {disabled} \ -CONFIG.PCW_MIO_8_SLEW {slow} \ -CONFIG.PCW_MIO_9_DIRECTION {out} \ -CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \ -CONFIG.PCW_MIO_9_PULLUP {enabled} \ -CONFIG.PCW_MIO_9_SLEW {slow} \ -CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#ENET Reset#GPIO#GPIO#GPIO#GPIO#UART 0#UART 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#GPIO#SD 0#UART 1#UART 1#GPIO#GPIO#Enet 0#Enet 0} \ -CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]#qspi0_sclk#gpio[7]#qspi_fbclk#reset#gpio[10]#gpio[11]#gpio[12]#gpio[13]#rx#tx#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#gpio[28]#gpio[29]#gpio[30]#gpio[31]#gpio[32]#gpio[33]#gpio[34]#gpio[35]#gpio[36]#gpio[37]#gpio[38]#gpio[39]#clk#cmd#data[0]#data[1]#data[2]#data[3]#gpio[46]#cd#tx#rx#gpio[50]#gpio[51]#mdc#mdio} \ -CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0 {0.223} \ -CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1 {0.212} \ -CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2 {0.085} \ -CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3 {0.092} \ -CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0 {0.040} \ -CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1 {0.058} \ -CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2 {-0.009} \ -CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3 {-0.033} \ -CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {5} \ -CONFIG.PCW_PERIPHERAL_BOARD_PRESET {part0} \ -CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \ -CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {1} \ -CONFIG.PCW_QSPI_GRP_FBCLK_IO {MIO 8} \ -CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \ -CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6} \ -CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {5} \ -CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \ -CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \ -CONFIG.PCW_SD0_GRP_CD_ENABLE {1} \ -CONFIG.PCW_SD0_GRP_CD_IO {MIO 47} \ -CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \ -CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45} \ -CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {20} \ -CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50} \ -CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \ -CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} \ -CONFIG.PCW_UART0_UART0_IO {MIO 14 .. 15} \ -CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \ -CONFIG.PCW_UART1_UART1_IO {MIO 48 .. 49} \ -CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {10} \ -CONFIG.PCW_UART_PERIPHERAL_VALID {1} \ -CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {525.000000} \ -CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.223} \ -CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.212} \ -CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.085} \ -CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.092} \ -CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {16 Bit} \ -CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM {25.8} \ -CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH {80.4535} \ -CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM {25.8} \ -CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH {80.4535} \ -CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH {80.4535} \ -CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH {80.4535} \ -CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \ -CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM {15.6} \ -CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH {105.056} \ -CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM {18.8} \ -CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH {66.904} \ -CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH {89.1715} \ -CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH {113.63} \ -CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.040} \ -CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.058} \ -CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {0.0} \ -CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {0.0} \ -CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM {16.5} \ -CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH {98.503} \ -CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM {18} \ -CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH {68.5855} \ -CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH {90.295} \ -CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH {103.977} \ -CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \ -CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {525} \ -CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41J256M16 RE-125} \ -CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \ -CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \ -CONFIG.PCW_UIPARAM_DDR_T_RC {48.91} \ -CONFIG.PCW_USB_RESET_ENABLE {1} \ -CONFIG.PCW_USE_M_AXI_GP0 {1} \ -CONFIG.PCW_USE_S_AXI_GP0 {0} \ -CONFIG.PCW_USE_S_AXI_HP0 {1} \ - ] $processing_system7_0 - - # Create instance: ps7_0_axi_periph, and set properties - set ps7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps7_0_axi_periph ] - set_property -dict [ list \ -CONFIG.NUM_MI {2} \ - ] $ps7_0_axi_periph - - # Create instance: rpm_check_0, and set properties - set rpm_check_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:rpm_check:1.0 rpm_check_0 ] - - # Create instance: rx_fifo, and set properties - set rx_fifo [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:1.1 rx_fifo ] - set_property -dict [ list \ -CONFIG.FIFO_DEPTH {512} \ -CONFIG.TDATA_NUM_BYTES {8} \ - ] $rx_fifo - - # Create instance: tx_fifo, and set properties - set tx_fifo [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:1.1 tx_fifo ] - set_property -dict [ list \ -CONFIG.FIFO_DEPTH {512} \ -CONFIG.TDATA_NUM_BYTES {8} \ - ] $tx_fifo - - # Create instance: xlconcat_0, and set properties - set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ] - set_property -dict [ list \ -CONFIG.NUM_PORTS {4} \ - ] $xlconcat_0 - - # Create instance: xlconcat_1, and set properties - set xlconcat_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_1 ] - set_property -dict [ list \ -CONFIG.IN0_WIDTH {4} \ -CONFIG.IN1_WIDTH {28} \ - ] $xlconcat_1 - - # Create instance: xlconstant_0, and set properties - set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] - set_property -dict [ list \ -CONFIG.CONST_VAL {0} \ -CONFIG.CONST_WIDTH {28} \ - ] $xlconstant_0 - - # Create instance: xlslice_0, and set properties - set xlslice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 ] - - # Create instance: xlslice_1, and set properties - set xlslice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_1 ] - set_property -dict [ list \ -CONFIG.DIN_FROM {3} \ -CONFIG.DOUT_WIDTH {4} \ - ] $xlslice_1 - - # Create instance: xlslice_2, and set properties - set xlslice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_2 ] - set_property -dict [ list \ -CONFIG.DIN_FROM {15} \ -CONFIG.DOUT_WIDTH {16} \ - ] $xlslice_2 - - # Create instance: xlslice_3, and set properties - set xlslice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_3 ] - set_property -dict [ list \ -CONFIG.DIN_FROM {19} \ -CONFIG.DIN_TO {4} \ -CONFIG.DOUT_WIDTH {16} \ - ] $xlslice_3 - - # Create instance: xlslice_4, and set properties - set xlslice_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_4 ] - set_property -dict [ list \ -CONFIG.DIN_FROM {20} \ -CONFIG.DIN_TO {20} \ -CONFIG.DOUT_WIDTH {1} \ - ] $xlslice_4 - - # Create instance: xlslice_5, and set properties - set xlslice_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_5 ] - set_property -dict [ list \ -CONFIG.DIN_FROM {21} \ -CONFIG.DIN_TO {21} \ -CONFIG.DOUT_WIDTH {1} \ - ] $xlslice_5 - - # Create instance: zero_16, and set properties - set zero_16 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 zero_16 ] - set_property -dict [ list \ -CONFIG.CONST_VAL {0} \ -CONFIG.CONST_WIDTH {16} \ - ] $zero_16 - - # Create interface connections - connect_bd_intf_net -intf_net AXI_StreamCapture_0_m_axis_s2mm [get_bd_intf_pins AXI_StreamCapture_0/m_axis_s2mm] [get_bd_intf_pins axi_datamover_0/S_AXIS_S2MM] - connect_bd_intf_net -intf_net AXI_StreamCapture_0_m_axis_s2mm_cmd [get_bd_intf_pins AXI_StreamCapture_0/m_axis_s2mm_cmd] [get_bd_intf_pins axi_datamover_0/S_AXIS_S2MM_CMD] - connect_bd_intf_net -intf_net Angle_RPM_Ib_Ia_m_axis [get_bd_intf_pins Angle_RPM_Ib_Ia/m_axis] [get_bd_intf_pins rx_fifo/S_AXIS] -connect_bd_intf_net -intf_net [get_bd_intf_nets Angle_RPM_Ib_Ia_m_axis] [get_bd_intf_pins axis_monitor_1/s00_axis] [get_bd_intf_pins rx_fifo/S_AXIS] -connect_bd_intf_net -intf_net Conn [get_bd_intf_pins FOC/s_axis_V1] [get_bd_intf_pins axis_monitor_1/s01_axis] -connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins FOC/SLOT_0_AXIS] [get_bd_intf_pins axis_monitor_1/s02_axis] -connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins FOC/m_axis] [get_bd_intf_pins axis_monitor_1/s03_axis] -connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins FOC/s_axis_V2] [get_bd_intf_pins axis_monitor_1/s04_axis] -connect_bd_intf_net -intf_net Conn4 [get_bd_intf_pins FOC/SLOT_0_AXIS1] [get_bd_intf_pins axis_monitor_1/s05_axis] - connect_bd_intf_net -intf_net FOC_m_axis_V [get_bd_intf_pins FOC/m_axis_V] [get_bd_intf_pins tx_fifo/S_AXIS] -connect_bd_intf_net -intf_net [get_bd_intf_nets FOC_m_axis_V] [get_bd_intf_pins axis_monitor_1/s06_axis] [get_bd_intf_pins tx_fifo/S_AXIS] - connect_bd_intf_net -intf_net axi_datamover_0_M_AXIS_S2MM_STS [get_bd_intf_pins AXI_StreamCapture_0/s_axis_s2mm_sts] [get_bd_intf_pins axi_datamover_0/M_AXIS_S2MM_STS] - connect_bd_intf_net -intf_net axi_datamover_0_M_AXI_S2MM [get_bd_intf_pins axi_datamover_0/M_AXI_S2MM] [get_bd_intf_pins axi_interconnect_0/S00_AXI] - connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_pins axi_interconnect_0/M00_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP0] - connect_bd_intf_net -intf_net axis_AD7403_0_m_axis [get_bd_intf_pins axis_AD7403_0/m_axis] [get_bd_intf_pins axis_data_fifo_1/S_AXIS] - connect_bd_intf_net -intf_net axis_data_fifo_0_M_AXIS [get_bd_intf_pins AXI_StreamCapture_0/s_axis] [get_bd_intf_pins axis_data_fifo_0/M_AXIS] - connect_bd_intf_net -intf_net axis_data_fifo_1_M_AXIS [get_bd_intf_pins Ib_Ia/S_AXIS] [get_bd_intf_pins axis_data_fifo_1/M_AXIS] - connect_bd_intf_net -intf_net axis_decimate_0_m_axis [get_bd_intf_pins axis_data_fifo_0/S_AXIS] [get_bd_intf_pins axis_decimate_0/m_axis] - connect_bd_intf_net -intf_net axis_encoder_0_m_angle [get_bd_intf_pins Angle_RPM_Ib_Ia/sc_axis] [get_bd_intf_pins axis_encoder_0/m_angle] - connect_bd_intf_net -intf_net axis_encoder_0_m_rpm [get_bd_intf_pins Angle_RPM_Ib_Ia/sb_axis] [get_bd_intf_pins axis_encoder_0/m_rpm] - connect_bd_intf_net -intf_net axis_monitor_1_m_axis [get_bd_intf_pins axis_decimate_0/s_axis] [get_bd_intf_pins axis_monitor_1/m_axis] - connect_bd_intf_net -intf_net axis_subset_converter_0_M_AXIS [get_bd_intf_pins Angle_RPM_Ib_Ia/sa_axis] [get_bd_intf_pins Ib_Ia/M_AXIS] - connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR] - connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO] - connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins ps7_0_axi_periph/S00_AXI] - connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI [get_bd_intf_pins axi_reg32_0/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M00_AXI] - connect_bd_intf_net -intf_net ps7_0_axi_periph_M01_AXI [get_bd_intf_pins AXI_StreamCapture_0/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M01_AXI] - connect_bd_intf_net -intf_net rx_fifo_M_AXIS [get_bd_intf_pins FOC/s_axis_V] [get_bd_intf_pins rx_fifo/M_AXIS] - connect_bd_intf_net -intf_net tx_fifo_M_AXIS [get_bd_intf_pins axis_pwm_0/S_AXIS] [get_bd_intf_pins tx_fifo/M_AXIS] - - # Create port connections - connect_bd_net -net A_1 [get_bd_ports ENC_A] [get_bd_pins axis_encoder_0/A] - connect_bd_net -net Angle_Shift_slice_Dout [get_bd_pins Angle_Shift_slice/Dout] [get_bd_pins axis_encoder_0/angle_shift] - connect_bd_net -net BTN0_1 [get_bd_ports BTN0] [get_bd_pins rpm_check_0/button] - connect_bd_net -net B_1 [get_bd_ports ENC_B] [get_bd_pins axis_encoder_0/B] - connect_bd_net -net FOC_Id_out [get_bd_pins FOC/Id_out] [get_bd_pins axi_reg32_0/RR2] - connect_bd_net -net FOC_Iq_out [get_bd_pins FOC/Iq_out] [get_bd_pins axi_reg32_0/RR3] - connect_bd_net -net FOC_dout [get_bd_pins FOC/RPM] [get_bd_pins axi_reg32_0/RR1] [get_bd_pins xlslice_2/Din] - connect_bd_net -net I_1 [get_bd_ports ENC_I] [get_bd_pins axis_encoder_0/I] - connect_bd_net -net SDI1_1 [get_bd_ports SDI1] [get_bd_pins xlconcat_0/In0] - connect_bd_net -net SDI2_1 [get_bd_ports SDI2] [get_bd_pins xlconcat_0/In1] - connect_bd_net -net SDI3_1 [get_bd_ports SDI3] [get_bd_pins xlconcat_0/In2] - connect_bd_net -net SDV_1 [get_bd_ports SDV] [get_bd_pins xlconcat_0/In3] - connect_bd_net -net SW0_1 [get_bd_ports SW0] [get_bd_pins clk_mux_0/sel] [get_bd_pins rpm_check_0/ss_in] - connect_bd_net -net Vq_1 [get_bd_pins FOC/Vq] [get_bd_pins axi_reg32_0/WR12] - connect_bd_net -net axi_reg32_0_WR0 [get_bd_pins FOC/control] [get_bd_pins axi_reg32_0/WR0] [get_bd_pins rpm_check_0/mode_in] - connect_bd_net -net axi_reg32_0_WR1 [get_bd_pins FOC/Flux_Sp] [get_bd_pins axi_reg32_0/WR1] - connect_bd_net -net axi_reg32_0_WR2 [get_bd_pins FOC/Flux_Kp] [get_bd_pins axi_reg32_0/WR2] - connect_bd_net -net axi_reg32_0_WR3 [get_bd_pins FOC/Flux_Ki] [get_bd_pins axi_reg32_0/WR3] - connect_bd_net -net axi_reg32_0_WR4 [get_bd_pins FOC/Torque_Sp] [get_bd_pins axi_reg32_0/WR4] - connect_bd_net -net axi_reg32_0_WR5 [get_bd_pins FOC/Torque_Kp] [get_bd_pins axi_reg32_0/WR5] - connect_bd_net -net axi_reg32_0_WR6 [get_bd_pins FOC/Torque_Ki] [get_bd_pins axi_reg32_0/WR6] - connect_bd_net -net axi_reg32_0_WR7 [get_bd_pins FOC/RPM_Sp] [get_bd_pins axi_reg32_0/WR7] - connect_bd_net -net axi_reg32_0_WR8 [get_bd_pins FOC/RPM_Kp] [get_bd_pins axi_reg32_0/WR8] - connect_bd_net -net axi_reg32_0_WR9 [get_bd_pins FOC/RPM_Ki] [get_bd_pins axi_reg32_0/WR9] - connect_bd_net -net axi_reg32_0_WR10 [get_bd_pins Angle_Shift_slice/Din] [get_bd_pins axi_reg32_0/WR10] - connect_bd_net -net axi_reg32_0_WR11 [get_bd_pins FOC/Vd] [get_bd_pins axi_reg32_0/WR11] - connect_bd_net -net axi_reg32_0_WR13 [get_bd_pins axi_reg32_0/WR13] [get_bd_pins axis_decimate_0/decimation] - connect_bd_net -net axi_reg32_0_WR14 [get_bd_pins axi_reg32_0/WR14] [get_bd_pins xlslice_0/Din] - connect_bd_net -net axi_reg32_0_WR15 [get_bd_pins axi_reg32_0/WR15] [get_bd_pins xlslice_1/Din] [get_bd_pins xlslice_3/Din] [get_bd_pins xlslice_4/Din] [get_bd_pins xlslice_5/Din] - connect_bd_net -net axis_AD7403_0_clkout [get_bd_ports SCLK] [get_bd_pins axis_AD7403_0/clkout] - connect_bd_net -net axis_encoder_0_angle_data [get_bd_pins Angle_concat/In0] [get_bd_pins axis_encoder_0/angle_data] - connect_bd_net -net axis_pwm_0_pwm_h [get_bd_ports GH] [get_bd_pins axis_pwm_0/pwm_h] - connect_bd_net -net axis_pwm_0_pwm_l [get_bd_ports GL] [get_bd_pins axis_pwm_0/pwm_l] - connect_bd_net -net clk_mux_0_clkout [get_bd_pins axis_AD7403_0/m_axis_aclk] [get_bd_pins axis_data_fifo_1/s_axis_aclk] [get_bd_pins clk_mux_0/clkout] [get_bd_pins proc_sys_reset_1/slowest_sync_clk] - connect_bd_net -net clk_wiz_0_clk_out1 [get_bd_pins clk_mux_0/clk1] [get_bd_pins clk_wiz_0/clk_out1] - connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins ps7_0_axi_periph/ARESETN] - connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins AXI_StreamCapture_0/axi_aresetn] [get_bd_pins Angle_RPM_Ib_Ia/s_axis_aresetn] [get_bd_pins FOC/ap_rst_n] [get_bd_pins Ib_Ia/aresetn] [get_bd_pins axi_datamover_0/m_axi_s2mm_aresetn] [get_bd_pins axi_datamover_0/m_axis_s2mm_cmdsts_aresetn] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_reg32_0/s_axi_aresetn] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins axis_data_fifo_1/m_axis_aresetn] [get_bd_pins axis_decimate_0/s_axis_aresetn] [get_bd_pins axis_encoder_0/axis_aresetn] [get_bd_pins axis_monitor_1/axis_aresetn] [get_bd_pins axis_pwm_0/s_axis_aresetn] [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/M01_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins rx_fifo/s_axis_aresetn] [get_bd_pins tx_fifo/s_axis_aresetn] - connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axis_AD7403_0/m_axis_aresetn] [get_bd_pins axis_data_fifo_1/s_axis_aresetn] [get_bd_pins proc_sys_reset_1/peripheral_aresetn] - connect_bd_net -net processing_system7_0_FCLK_CLK1 [get_bd_pins AXI_StreamCapture_0/axi_aclk] [get_bd_pins Angle_RPM_Ib_Ia/s_axis_aclk] [get_bd_pins FOC/ap_clk] [get_bd_pins Ib_Ia/aclk] [get_bd_pins axi_datamover_0/m_axi_s2mm_aclk] [get_bd_pins axi_datamover_0/m_axis_s2mm_cmdsts_awclk] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins axi_reg32_0/s_axi_aclk] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins axis_data_fifo_1/m_axis_aclk] [get_bd_pins axis_decimate_0/s_axis_aclk] [get_bd_pins axis_encoder_0/axis_aclk] [get_bd_pins axis_monitor_1/axis_aclk] [get_bd_pins axis_pwm_0/s_axis_aclk] [get_bd_pins clk_mux_0/clk0] [get_bd_pins clk_wiz_0/clk_in1] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/M01_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins rpm_check_0/aclk] [get_bd_pins rx_fifo/s_axis_aclk] [get_bd_pins tx_fifo/s_axis_aclk] - connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins proc_sys_reset_0/ext_reset_in] [get_bd_pins proc_sys_reset_1/ext_reset_in] [get_bd_pins processing_system7_0/FCLK_RESET0_N] - connect_bd_net -net rpm_check_0_led [get_bd_ports led] [get_bd_pins rpm_check_0/led] [get_bd_pins xlconcat_1/In0] - connect_bd_net -net xlconcat_0_dout [get_bd_pins axis_AD7403_0/din] [get_bd_pins xlconcat_0/dout] - connect_bd_net -net xlconcat_1_dout [get_bd_pins Angle_concat/dout] [get_bd_pins axi_reg32_0/RR0] - connect_bd_net -net xlconcat_1_dout1 [get_bd_pins axi_reg32_0/RR4] [get_bd_pins xlconcat_1/dout] - connect_bd_net -net xlconstant_0_dout [get_bd_pins xlconcat_1/In1] [get_bd_pins xlconstant_0/dout] - connect_bd_net -net xlslice_1_Dout [get_bd_pins axis_monitor_1/mux_in] [get_bd_pins xlslice_1/Dout] - connect_bd_net -net xlslice_2_Dout [get_bd_pins rpm_check_0/rpm_data] [get_bd_pins xlslice_2/Dout] - connect_bd_net -net xlslice_3_Dout [get_bd_pins rpm_check_0/tolerance_in] [get_bd_pins xlslice_3/Dout] - connect_bd_net -net xlslice_4_Dout [get_bd_pins rpm_check_0/led_in] [get_bd_pins xlslice_4/Dout] - connect_bd_net -net xlslice_5_Dout [get_bd_pins rpm_check_0/restart_in] [get_bd_pins xlslice_5/Dout] - connect_bd_net -net zero_16_dout [get_bd_pins Angle_concat/In1] [get_bd_pins zero_16/dout] - - # Create address segments - create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces axi_datamover_0/Data_S2MM] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_HP0_DDR_LOWOCM - create_bd_addr_seg -range 0x00010000 -offset 0x43C10000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs AXI_StreamCapture_0/S_AXI/S_AXI_reg] SEG_AXI_StreamCapture_0_S_AXI_reg - create_bd_addr_seg -range 0x00010000 -offset 0x43C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_reg32_0/S_AXI/S_AXI_reg] SEG_axi_reg32_0_S_AXI_reg - - - # Restore current instance - current_bd_instance $oldCurInst - - save_bd_design -} -# End of create_root_design() +read_xdc C:/Users/ga53xem/IIoT-EDDP/myWS/VivadoProjects/my_FOC/my_FOC.srcs/constrs_1/imports/constraints/vivado_target.xdc +set_property used_in_implementation false [get_files C:/Users/ga53xem/IIoT-EDDP/myWS/VivadoProjects/my_FOC/my_FOC.srcs/constrs_1/imports/constraints/vivado_target.xdc] +read_xdc dont_touch.xdc +set_property used_in_implementation false [get_files dont_touch.xdc] -################################################################## -# MAIN FLOW -################################################################## +synth_design -top zsys_wrapper -part xc7z020clg400-1 -create_root_design "" +write_checkpoint -force -noxdef zsys_wrapper.dcp +catch { report_utilization -file zsys_wrapper_utilization_synth.rpt -pb zsys_wrapper_utilization_synth.pb } diff --git a/boards/Pynq-Z2/__init__.py b/boards/Pynq-Z2/__init__.py deleted file mode 100644 index 00c9436..0000000 --- a/boards/Pynq-Z2/__init__.py +++ /dev/null @@ -1,35 +0,0 @@ -# Copyright (c) 2018, Xilinx, Inc. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# 1. Redistributions of source code must retain the above copyright notice, -# this list of conditions and the following disclaimer. -# -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# -# 3. Neither the name of the copyright holder nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR -# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; -# OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR -# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - - -__author__ = "KV Thanjavur Bhaaskar, Naveen Purushotham" -__copyright__ = "Copyright 2018, Xilinx" -__email__ = "kvt@xilinx.com, npurusho@xilinx.com" - -from .spyn import SpynOverlay diff --git a/boards/Pynq-Z2/spyn.bit b/boards/Pynq-Z2/spyn.bit deleted file mode 100644 index c42d2c2..0000000 Binary files a/boards/Pynq-Z2/spyn.bit and /dev/null differ diff --git a/boards/Pynq-Z2/spyn.hwh b/boards/Pynq-Z2/spyn.hwh deleted file mode 100644 index 2c4d320..0000000 --- a/boards/Pynq-Z2/spyn.hwh +++ /dev/null @@ -1,8807 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/boards/Pynq-Z2/spyn.tcl b/boards/Pynq-Z2/spyn.tcl deleted file mode 100644 index 0cdc9c6..0000000 --- a/boards/Pynq-Z2/spyn.tcl +++ /dev/null @@ -1,1140 +0,0 @@ - -################################################################ -# This is a generated script based on design: zsys -# -# Though there are limitations about the generated script, -# the main purpose of this utility is to make learning -# IP Integrator Tcl commands easier. -################################################################ - -namespace eval _tcl { -proc get_script_folder {} { - set script_path [file normalize [info script]] - set script_folder [file dirname $script_path] - return $script_folder -} -} -variable script_folder -set script_folder [_tcl::get_script_folder] - -################################################################ -# Check if script is running in correct Vivado version. -################################################################ -set scripts_vivado_version 2017.1 -set current_vivado_version [version -short] - -if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { - puts "" - catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} - - return 1 -} - -################################################################ -# START -################################################################ - -# To test this script, run the following commands from Vivado Tcl console: -# source zsys_script.tcl - -# If there is no project opened, this script will create a -# project, but make sure you do not have an existing project -# <./myproj/project_1.xpr> in the current working folder. - -set list_projs [get_projects -quiet] -if { $list_projs eq "" } { - create_project project_1 myproj -part xc7z020clg400-1 - set_property BOARD_PART tul.com.tw:pynq-z2:part0:1.0 [current_project] -} - - -# CHANGE DESIGN NAME HERE -set design_name zsys - -# If you do not already have an existing IP Integrator design open, -# you can create a design using the following command: -# create_bd_design $design_name - -# Creating design if needed -set errMsg "" -set nRet 0 - -set cur_design [current_bd_design -quiet] -set list_cells [get_bd_cells -quiet] - -if { ${design_name} eq "" } { - # USE CASES: - # 1) Design_name not set - - set errMsg "Please set the variable to a non-empty value." - set nRet 1 - -} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { - # USE CASES: - # 2): Current design opened AND is empty AND names same. - # 3): Current design opened AND is empty AND names diff; design_name NOT in project. - # 4): Current design opened AND is empty AND names diff; design_name exists in project. - - if { $cur_design ne $design_name } { - common::send_msg_id "BD_TCL-001" "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." - set design_name [get_property NAME $cur_design] - } - common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." - -} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { - # USE CASES: - # 5) Current design opened AND has components AND same names. - - set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." - set nRet 1 -} elseif { [get_files -quiet ${design_name}.bd] ne "" } { - # USE CASES: - # 6) Current opened design, has components, but diff names, design_name exists in project. - # 7) No opened design, design_name exists in project. - - set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." - set nRet 2 - -} else { - # USE CASES: - # 8) No opened design, design_name not in project. - # 9) Current opened design, has components, but diff names, design_name not in project. - - common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." - - create_bd_design $design_name - - common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." - current_bd_design $design_name - -} - -common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable is equal to \"$design_name\"." - -if { $nRet != 0 } { - catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} - return $nRet -} - -################################################################## -# DESIGN PROCs -################################################################## - - -# Hierarchical cell: FOC -proc create_hier_cell_FOC { parentCell nameHier } { - - variable script_folder - - if { $parentCell eq "" || $nameHier eq "" } { - catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_FOC() - Empty argument(s)!"} - return - } - - # Get object for parentCell - set parentObj [get_bd_cells $parentCell] - if { $parentObj == "" } { - catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} - return - } - - # Make sure parentObj is hier blk - set parentType [get_property TYPE $parentObj] - if { $parentType ne "hier" } { - catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} - return - } - - # Save current instance; Restore later - set oldCurInst [current_bd_instance .] - - # Set parent object as current - current_bd_instance $parentObj - - # Create cell and set as current instance - set hier_obj [create_bd_cell -type hier $nameHier] - current_bd_instance $hier_obj - - # Create interface pins - create_bd_intf_pin -mode Monitor -vlnv xilinx.com:interface:axis_rtl:1.0 SLOT_0_AXIS - create_bd_intf_pin -mode Monitor -vlnv xilinx.com:interface:axis_rtl:1.0 SLOT_0_AXIS1 - create_bd_intf_pin -mode Monitor -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis - create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_V - create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_V - create_bd_intf_pin -mode Monitor -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_V1 - create_bd_intf_pin -mode Monitor -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_V2 - - # Create pins - create_bd_pin -dir I -from 31 -to 0 Flux_Ki - create_bd_pin -dir I -from 31 -to 0 Flux_Kp - create_bd_pin -dir I -from 31 -to 0 Flux_Sp - create_bd_pin -dir O -from 31 -to 0 -type data Id_out - create_bd_pin -dir O -from 31 -to 0 -type data Iq_out - create_bd_pin -dir O -from 31 -to 0 RPM - create_bd_pin -dir I -from 31 -to 0 RPM_Ki - create_bd_pin -dir I -from 31 -to 0 RPM_Kp - create_bd_pin -dir I -from 31 -to 0 RPM_Sp - create_bd_pin -dir I -from 31 -to 0 Torque_Ki - create_bd_pin -dir I -from 31 -to 0 Torque_Kp - create_bd_pin -dir I -from 31 -to 0 Torque_Sp - create_bd_pin -dir I -from 31 -to 0 Vd - create_bd_pin -dir I -from 31 -to 0 Vq - create_bd_pin -dir I -type clk ap_clk - create_bd_pin -dir I -type rst ap_rst_n - create_bd_pin -dir I -from 31 -to 0 -type data control - - # Create instance: Clarke_Direct_0, and set properties - set Clarke_Direct_0 [ create_bd_cell -type ip -vlnv trenz.biz:hls:Clarke_Direct:1.0 Clarke_Direct_0 ] - - # Create instance: Clarke_Inverse_0, and set properties - set Clarke_Inverse_0 [ create_bd_cell -type ip -vlnv trenz.biz:hls:Clarke_Inverse:1.0 Clarke_Inverse_0 ] - - # Create instance: Filters_0, and set properties - set Filters_0 [ create_bd_cell -type ip -vlnv trenz.biz:hls:Filters:1.0 Filters_0 ] - - # Create instance: Flux_Ki_slice, and set properties - set Flux_Ki_slice [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 Flux_Ki_slice ] - set_property -dict [ list \ -CONFIG.DIN_FROM {15} \ -CONFIG.DOUT_WIDTH {16} \ - ] $Flux_Ki_slice - - # Create instance: Flux_Kp_slice, and set properties - set Flux_Kp_slice [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 Flux_Kp_slice ] - set_property -dict [ list \ -CONFIG.DIN_FROM {15} \ -CONFIG.DOUT_WIDTH {16} \ - ] $Flux_Kp_slice - - # Create instance: Flux_PI_Control, and set properties - set Flux_PI_Control [ create_bd_cell -type ip -vlnv trenz.biz:hls:PI_Control:1.0 Flux_PI_Control ] - - # Create instance: Flux_Sp_slice, and set properties - set Flux_Sp_slice [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 Flux_Sp_slice ] - set_property -dict [ list \ -CONFIG.DIN_FROM {15} \ -CONFIG.DOUT_WIDTH {16} \ - ] $Flux_Sp_slice - - # Create instance: Park_Direct_0, and set properties - set Park_Direct_0 [ create_bd_cell -type ip -vlnv trenz.biz:hls:Park_Direct:1.0 Park_Direct_0 ] - - # Create instance: Park_Inverse_0, and set properties - set Park_Inverse_0 [ create_bd_cell -type ip -vlnv trenz.biz:hls:Park_Inverse:1.0 Park_Inverse_0 ] - - # Create instance: RPM_Ki_slice, and set properties - set RPM_Ki_slice [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 RPM_Ki_slice ] - set_property -dict [ list \ -CONFIG.DIN_FROM {15} \ -CONFIG.DOUT_WIDTH {16} \ - ] $RPM_Ki_slice - - # Create instance: RPM_Kp_slice, and set properties - set RPM_Kp_slice [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 RPM_Kp_slice ] - set_property -dict [ list \ -CONFIG.DIN_FROM {15} \ -CONFIG.DOUT_WIDTH {16} \ - ] $RPM_Kp_slice - - # Create instance: RPM_PI_Control, and set properties - set RPM_PI_Control [ create_bd_cell -type ip -vlnv trenz.biz:hls:PI_Control:1.0 RPM_PI_Control ] - - # Create instance: RPM_Sp_slice, and set properties - set RPM_Sp_slice [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 RPM_Sp_slice ] - set_property -dict [ list \ -CONFIG.DIN_FROM {15} \ -CONFIG.DOUT_WIDTH {16} \ - ] $RPM_Sp_slice - - # Create instance: SVPWM_0, and set properties - set SVPWM_0 [ create_bd_cell -type ip -vlnv trenz.biz:hls:SVPWM:1.0 SVPWM_0 ] - - # Create instance: Torque_Ki_slice, and set properties - set Torque_Ki_slice [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 Torque_Ki_slice ] - set_property -dict [ list \ -CONFIG.DIN_FROM {15} \ -CONFIG.DOUT_WIDTH {16} \ - ] $Torque_Ki_slice - - # Create instance: Torque_Kp_slice, and set properties - set Torque_Kp_slice [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 Torque_Kp_slice ] - set_property -dict [ list \ -CONFIG.DIN_FROM {15} \ -CONFIG.DOUT_WIDTH {16} \ - ] $Torque_Kp_slice - - # Create instance: Torque_PI_Control, and set properties - set Torque_PI_Control [ create_bd_cell -type ip -vlnv trenz.biz:hls:PI_Control:1.0 Torque_PI_Control ] - - # Create instance: Torque_Sp_slice, and set properties - set Torque_Sp_slice [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 Torque_Sp_slice ] - set_property -dict [ list \ -CONFIG.DIN_FROM {15} \ -CONFIG.DOUT_WIDTH {16} \ - ] $Torque_Sp_slice - - # Create instance: axis_broadcaster_0, and set properties - set axis_broadcaster_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_broadcaster:1.1 axis_broadcaster_0 ] - set_property -dict [ list \ -CONFIG.M00_TDATA_REMAP {tdata[15:0]} \ -CONFIG.M01_TDATA_REMAP {tdata[31:16]} \ -CONFIG.M02_TDATA_REMAP {tdata[47:32]} \ -CONFIG.M03_TDATA_REMAP {tdata[63:48]} \ -CONFIG.M_TDATA_NUM_BYTES {2} \ -CONFIG.NUM_MI {4} \ -CONFIG.S_TDATA_NUM_BYTES {8} \ - ] $axis_broadcaster_0 - - # Create instance: flux_limit, and set properties - set flux_limit [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 flux_limit ] - set_property -dict [ list \ -CONFIG.CONST_VAL {16777215} \ -CONFIG.CONST_WIDTH {32} \ - ] $flux_limit - - # Create instance: foc_control_0, and set properties - set foc_control_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:foc_control:1.0 foc_control_0 ] - - # Create instance: one, and set properties - set one [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 one ] - - # Create instance: rpm_limit, and set properties - set rpm_limit [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 rpm_limit ] - set_property -dict [ list \ -CONFIG.CONST_VAL {16777215} \ -CONFIG.CONST_WIDTH {32} \ - ] $rpm_limit - - # Create instance: torque_limit, and set properties - set torque_limit [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 torque_limit ] - set_property -dict [ list \ -CONFIG.CONST_VAL {16777215} \ -CONFIG.CONST_WIDTH {32} \ - ] $torque_limit - - # Create interface connections - connect_bd_intf_net -intf_net Clarke_Direct_0_m_axis_V [get_bd_intf_pins Clarke_Direct_0/m_axis_V] [get_bd_intf_pins Park_Direct_0/s_axis_V] - connect_bd_intf_net -intf_net [get_bd_intf_nets Clarke_Direct_0_m_axis_V] [get_bd_intf_pins s_axis_V1] [get_bd_intf_pins Clarke_Direct_0/m_axis_V] - connect_bd_intf_net -intf_net Clarke_Inverse_0_m_axis_V [get_bd_intf_pins Clarke_Inverse_0/m_axis_V] [get_bd_intf_pins SVPWM_0/s_axis_V] - connect_bd_intf_net -intf_net [get_bd_intf_nets Clarke_Inverse_0_m_axis_V] [get_bd_intf_pins SLOT_0_AXIS1] [get_bd_intf_pins Clarke_Inverse_0/m_axis_V] - connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins s_axis_V] [get_bd_intf_pins Filters_0/s_axis_V] - connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins m_axis_V] [get_bd_intf_pins SVPWM_0/m_axis_V] - connect_bd_intf_net -intf_net Filters_0_m_axis_V [get_bd_intf_pins Clarke_Direct_0/s_axis_V] [get_bd_intf_pins Filters_0/m_axis_V] - connect_bd_intf_net -intf_net Flux_PI_Control_m_axis_V [get_bd_intf_pins Flux_PI_Control/m_axis_V] [get_bd_intf_pins foc_control_0/s_flux] - connect_bd_intf_net -intf_net Park_Direct_0_m_axis_V [get_bd_intf_pins Park_Direct_0/m_axis_V] [get_bd_intf_pins axis_broadcaster_0/S_AXIS] - connect_bd_intf_net -intf_net [get_bd_intf_nets Park_Direct_0_m_axis_V] [get_bd_intf_pins SLOT_0_AXIS] [get_bd_intf_pins axis_broadcaster_0/S_AXIS] - connect_bd_intf_net -intf_net Park_Inverse_0_m_axis_V [get_bd_intf_pins Clarke_Inverse_0/s_axis_V] [get_bd_intf_pins Park_Inverse_0/m_axis_V] - connect_bd_intf_net -intf_net [get_bd_intf_nets Park_Inverse_0_m_axis_V] [get_bd_intf_pins s_axis_V2] [get_bd_intf_pins Park_Inverse_0/m_axis_V] - connect_bd_intf_net -intf_net RPM_PI_Control_m_axis_V [get_bd_intf_pins RPM_PI_Control/m_axis_V] [get_bd_intf_pins foc_control_0/s_rpm] - connect_bd_intf_net -intf_net Torque_PI_Control_m_axis_V [get_bd_intf_pins Torque_PI_Control/m_axis_V] [get_bd_intf_pins foc_control_0/s_torque] - connect_bd_intf_net -intf_net axis_broadcaster_0_M00_AXIS [get_bd_intf_pins Flux_PI_Control/s_axis_V] [get_bd_intf_pins axis_broadcaster_0/M00_AXIS] - connect_bd_intf_net -intf_net axis_broadcaster_0_M01_AXIS [get_bd_intf_pins Torque_PI_Control/s_axis_V] [get_bd_intf_pins axis_broadcaster_0/M01_AXIS] - connect_bd_intf_net -intf_net axis_broadcaster_0_M02_AXIS [get_bd_intf_pins RPM_PI_Control/s_axis_V] [get_bd_intf_pins axis_broadcaster_0/M02_AXIS] - connect_bd_intf_net -intf_net axis_broadcaster_0_M03_AXIS [get_bd_intf_pins axis_broadcaster_0/M03_AXIS] [get_bd_intf_pins foc_control_0/s_angle] - connect_bd_intf_net -intf_net foc_control_0_m_axis [get_bd_intf_pins Park_Inverse_0/s_axis_V] [get_bd_intf_pins foc_control_0/m_axis] - connect_bd_intf_net -intf_net [get_bd_intf_nets foc_control_0_m_axis] [get_bd_intf_pins m_axis] [get_bd_intf_pins foc_control_0/m_axis] - - # Create port connections - connect_bd_net -net Din1_1 [get_bd_pins RPM_Kp] [get_bd_pins RPM_Kp_slice/Din] - connect_bd_net -net Din2_1 [get_bd_pins RPM_Ki] [get_bd_pins RPM_Ki_slice/Din] - connect_bd_net -net Din3_1 [get_bd_pins Flux_Sp] [get_bd_pins Flux_Sp_slice/Din] - connect_bd_net -net Din4_1 [get_bd_pins Flux_Kp] [get_bd_pins Flux_Kp_slice/Din] - connect_bd_net -net Din5_1 [get_bd_pins Flux_Ki] [get_bd_pins Flux_Ki_slice/Din] - connect_bd_net -net Din6_1 [get_bd_pins Torque_Kp] [get_bd_pins Torque_Kp_slice/Din] - connect_bd_net -net Din7_1 [get_bd_pins Torque_Ki] [get_bd_pins Torque_Ki_slice/Din] - connect_bd_net -net Din_1 [get_bd_pins RPM_Sp] [get_bd_pins RPM_Sp_slice/Din] - connect_bd_net -net Filters_0_RPM_out [get_bd_pins RPM] [get_bd_pins Filters_0/RPM_out] - connect_bd_net -net Flux_Ki_slice_Dout [get_bd_pins Flux_Ki_slice/Dout] [get_bd_pins Flux_PI_Control/Ki] - connect_bd_net -net Flux_Kp_slice_Dout [get_bd_pins Flux_Kp_slice/Dout] [get_bd_pins Flux_PI_Control/Kp] - connect_bd_net -net Flux_Sp_slice_Dout [get_bd_pins Flux_PI_Control/Sp] [get_bd_pins Flux_Sp_slice/Dout] - connect_bd_net -net Park_Direct_0_Id_out [get_bd_pins Id_out] [get_bd_pins Park_Direct_0/Id_out] - connect_bd_net -net Park_Direct_0_Iq_out [get_bd_pins Iq_out] [get_bd_pins Park_Direct_0/Iq_out] - connect_bd_net -net RPM_Ki_slice_Dout [get_bd_pins RPM_Ki_slice/Dout] [get_bd_pins RPM_PI_Control/Ki] - connect_bd_net -net RPM_Kp_slice_Dout [get_bd_pins RPM_Kp_slice/Dout] [get_bd_pins RPM_PI_Control/Kp] - connect_bd_net -net RPM_Sp_slice_Dout [get_bd_pins RPM_PI_Control/Sp] [get_bd_pins RPM_Sp_slice/Dout] - connect_bd_net -net Torque_Ki_slice_Dout [get_bd_pins Torque_Ki_slice/Dout] [get_bd_pins Torque_PI_Control/Ki] - connect_bd_net -net Torque_Kp_slice_Dout [get_bd_pins Torque_Kp_slice/Dout] [get_bd_pins Torque_PI_Control/Kp] - connect_bd_net -net Torque_Sp_1 [get_bd_pins Torque_Sp] [get_bd_pins Torque_Sp_slice/Din] - connect_bd_net -net Torque_Sp_slice_Dout [get_bd_pins Torque_Sp_slice/Dout] [get_bd_pins foc_control_0/torque_sp_in] - connect_bd_net -net Vd_1 [get_bd_pins Vd] [get_bd_pins foc_control_0/vd_in] - connect_bd_net -net Vq_1 [get_bd_pins Vq] [get_bd_pins foc_control_0/vq_in] - connect_bd_net -net ap_clk_1 [get_bd_pins ap_clk] [get_bd_pins Clarke_Direct_0/ap_clk] [get_bd_pins Clarke_Inverse_0/ap_clk] [get_bd_pins Filters_0/ap_clk] [get_bd_pins Flux_PI_Control/ap_clk] [get_bd_pins Park_Direct_0/ap_clk] [get_bd_pins Park_Inverse_0/ap_clk] [get_bd_pins RPM_PI_Control/ap_clk] [get_bd_pins SVPWM_0/ap_clk] [get_bd_pins Torque_PI_Control/ap_clk] [get_bd_pins axis_broadcaster_0/aclk] [get_bd_pins foc_control_0/axis_aclk] - connect_bd_net -net ap_rst_n_1 [get_bd_pins ap_rst_n] [get_bd_pins Clarke_Direct_0/ap_rst_n] [get_bd_pins Clarke_Inverse_0/ap_rst_n] [get_bd_pins Filters_0/ap_rst_n] [get_bd_pins Flux_PI_Control/ap_rst_n] [get_bd_pins Park_Direct_0/ap_rst_n] [get_bd_pins Park_Inverse_0/ap_rst_n] [get_bd_pins RPM_PI_Control/ap_rst_n] [get_bd_pins SVPWM_0/ap_rst_n] [get_bd_pins Torque_PI_Control/ap_rst_n] [get_bd_pins axis_broadcaster_0/aresetn] [get_bd_pins foc_control_0/axis_aresetn] - connect_bd_net -net control_1 [get_bd_pins control] [get_bd_pins Filters_0/control] [get_bd_pins Flux_PI_Control/mode] [get_bd_pins RPM_PI_Control/mode] [get_bd_pins Torque_PI_Control/mode] [get_bd_pins foc_control_0/control_in] - connect_bd_net -net flux_limit_dout [get_bd_pins Flux_PI_Control/limit] [get_bd_pins flux_limit/dout] - connect_bd_net -net foc_control_0_torque_sp_out [get_bd_pins Torque_PI_Control/Sp] [get_bd_pins foc_control_0/torque_sp_out] - connect_bd_net -net one_dout [get_bd_pins Clarke_Direct_0/ap_start] [get_bd_pins Clarke_Inverse_0/ap_start] [get_bd_pins Filters_0/ap_start] [get_bd_pins Flux_PI_Control/ap_start] [get_bd_pins Park_Direct_0/ap_start] [get_bd_pins Park_Inverse_0/ap_start] [get_bd_pins RPM_PI_Control/ap_start] [get_bd_pins SVPWM_0/ap_start] [get_bd_pins Torque_PI_Control/ap_start] [get_bd_pins one/dout] - connect_bd_net -net rpm_limit_dout [get_bd_pins RPM_PI_Control/limit] [get_bd_pins rpm_limit/dout] - connect_bd_net -net torque_limit_dout [get_bd_pins Torque_PI_Control/limit] [get_bd_pins torque_limit/dout] - - # Restore current instance - current_bd_instance $oldCurInst -} - - -# Procedure to create entire design; Provide argument to make -# procedure reusable. If parentCell is "", will use root. -proc create_root_design { parentCell } { - - variable script_folder - - if { $parentCell eq "" } { - set parentCell [get_bd_cells /] - } - - # Get object for parentCell - set parentObj [get_bd_cells $parentCell] - if { $parentObj == "" } { - catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} - return - } - - # Make sure parentObj is hier blk - set parentType [get_property TYPE $parentObj] - if { $parentType ne "hier" } { - catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} - return - } - - # Save current instance; Restore later - set oldCurInst [current_bd_instance .] - - # Set parent object as current - current_bd_instance $parentObj - - - # Create interface ports - set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ] - set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ] - - # Create ports - set BTN0 [ create_bd_port -dir I BTN0 ] - set ENC_A [ create_bd_port -dir I ENC_A ] - set ENC_B [ create_bd_port -dir I ENC_B ] - set ENC_I [ create_bd_port -dir I ENC_I ] - set GH [ create_bd_port -dir O -from 2 -to 0 GH ] - set GL [ create_bd_port -dir O -from 2 -to 0 GL ] - set SCLK [ create_bd_port -dir O SCLK ] - set SDI1 [ create_bd_port -dir I SDI1 ] - set SDI2 [ create_bd_port -dir I SDI2 ] - set SDI3 [ create_bd_port -dir I SDI3 ] - set SDV [ create_bd_port -dir I SDV ] - set SW0 [ create_bd_port -dir I SW0 ] - set led [ create_bd_port -dir O -from 3 -to 0 led ] - - # Create instance: AXI_StreamCapture_0, and set properties - set AXI_StreamCapture_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:AXI_StreamCapture:1.0 AXI_StreamCapture_0 ] - - # Create instance: Angle_RPM_Ib_Ia, and set properties - set Angle_RPM_Ib_Ia [ create_bd_cell -type ip -vlnv trenz.biz:user:axis_concat:1.0 Angle_RPM_Ib_Ia ] - set_property -dict [ list \ -CONFIG.C_A_TDATA_WIDTH {32} \ -CONFIG.C_IN_CHANNELS {3} \ -CONFIG.M_TDATA_WIDTH {64} \ - ] $Angle_RPM_Ib_Ia - - # Create instance: Angle_Shift_slice, and set properties - set Angle_Shift_slice [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 Angle_Shift_slice ] - set_property -dict [ list \ -CONFIG.DIN_FROM {15} \ -CONFIG.DOUT_WIDTH {16} \ - ] $Angle_Shift_slice - - # Create instance: Angle_concat, and set properties - set Angle_concat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 Angle_concat ] - set_property -dict [ list \ -CONFIG.IN0_WIDTH {16} \ -CONFIG.IN1_WIDTH {16} \ - ] $Angle_concat - - # Create instance: FOC - create_hier_cell_FOC [current_bd_instance .] FOC - - # Create instance: Ib_Ia, and set properties - set Ib_Ia [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_subset_converter:1.1 Ib_Ia ] - set_property -dict [ list \ -CONFIG.M_TDATA_NUM_BYTES {4} \ -CONFIG.S_TDATA_NUM_BYTES {8} \ -CONFIG.TDATA_REMAP {tdata[31:0]} \ - ] $Ib_Ia - - # Create instance: axi_datamover_0, and set properties - set axi_datamover_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_datamover:5.1 axi_datamover_0 ] - set_property -dict [ list \ -CONFIG.c_enable_mm2s {0} \ -CONFIG.c_include_mm2s {Omit} \ -CONFIG.c_include_mm2s_stsfifo {false} \ -CONFIG.c_m_axi_s2mm_id_width {0} \ -CONFIG.c_mm2s_include_sf {false} \ -CONFIG.c_s2mm_btt_used {23} \ -CONFIG.c_s2mm_burst_size {8} \ -CONFIG.c_s2mm_include_sf {false} \ -CONFIG.c_s2mm_support_indet_btt {true} \ - ] $axi_datamover_0 - - # Create instance: axi_interconnect_0, and set properties - set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ] - set_property -dict [ list \ -CONFIG.NUM_MI {1} \ - ] $axi_interconnect_0 - - # Create instance: axi_reg32_0, and set properties - set axi_reg32_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:axi_reg32:1.0 axi_reg32_0 ] - set_property -dict [ list \ -CONFIG.C_NUM_RO_REG {5} \ -CONFIG.C_NUM_WR_REG {16} \ -CONFIG.C_WR0_ALIAS {Control} \ -CONFIG.C_WR10_ALIAS {Angle Shift} \ -CONFIG.C_WR10_DEFAULT {719} \ -CONFIG.C_WR11_ALIAS {Vd} \ -CONFIG.C_WR11_DEFAULT {-7424} \ -CONFIG.C_WR12_ALIAS {Vq} \ -CONFIG.C_WR12_DEFAULT {15000} \ -CONFIG.C_WR13_ALIAS {Decimation} \ -CONFIG.C_WR14_ALIAS {TR_Control} \ -CONFIG.C_WR1_ALIAS {Flux Sp} \ -CONFIG.C_WR2_ALIAS {Flux Kp} \ -CONFIG.C_WR2_DEFAULT {-45056} \ -CONFIG.C_WR3_ALIAS {Flux Ki} \ -CONFIG.C_WR4_ALIAS {Torque Sp} \ -CONFIG.C_WR4_DEFAULT {100} \ -CONFIG.C_WR5_ALIAS {Torque Kp} \ -CONFIG.C_WR5_DEFAULT {256} \ -CONFIG.C_WR6_ALIAS {Torque Ki} \ -CONFIG.C_WR7_ALIAS {RPM Sp} \ -CONFIG.C_WR7_DEFAULT {3000} \ -CONFIG.C_WR8_ALIAS {RPM Kp} \ -CONFIG.C_WR8_DEFAULT {744} \ -CONFIG.C_WR9_ALIAS {RPM Ki} \ -CONFIG.C_WR9_DEFAULT {9} \ - ] $axi_reg32_0 - - # Create instance: axis_AD7403_0, and set properties - set axis_AD7403_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:axis_AD7403:1.0 axis_AD7403_0 ] - set_property -dict [ list \ -CONFIG.C_CLOCK_RATIO {5} \ -CONFIG.C_DECIMATION {128} \ -CONFIG.C_SIGNED {true} \ - ] $axis_AD7403_0 - - # Create instance: axis_data_fifo_0, and set properties - set axis_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:1.1 axis_data_fifo_0 ] - set_property -dict [ list \ -CONFIG.FIFO_DEPTH {4096} \ - ] $axis_data_fifo_0 - - # Create instance: axis_data_fifo_1, and set properties - set axis_data_fifo_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:1.1 axis_data_fifo_1 ] - set_property -dict [ list \ -CONFIG.IS_ACLK_ASYNC {1} \ - ] $axis_data_fifo_1 - - # Create instance: axis_decimate_0, and set properties - set axis_decimate_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:axis_decimate:1.0 axis_decimate_0 ] - set_property -dict [ list \ -CONFIG.C_TDATA_WIDTH {64} \ - ] $axis_decimate_0 - - # Create instance: axis_encoder_0, and set properties - set axis_encoder_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:axis_encoder:1.0 axis_encoder_0 ] - set_property -dict [ list \ -CONFIG.C_ANGLE_AXIS {true} \ -CONFIG.C_CPR {1000} \ -CONFIG.C_RPM_AXIS {true} \ -CONFIG.C_USE_SHIFT {true} \ - ] $axis_encoder_0 - - # Create instance: axis_monitor_1, and set properties - set axis_monitor_1 [ create_bd_cell -type ip -vlnv trenz.biz:user:axis_monitor:1.1 axis_monitor_1 ] - set_property -dict [ list \ -CONFIG.C_SLAVE_IF {7} \ - ] $axis_monitor_1 - - # Create instance: axis_pwm_0, and set properties - set axis_pwm_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:axis_pwm:1.0 axis_pwm_0 ] - set_property -dict [ list \ -CONFIG.C_CHANNELS {3} \ -CONFIG.C_DEADTIME_SYCLES {50} \ -CONFIG.C_IN_TYPE {1} \ -CONFIG.C_S_AXIS_TDATA_WIDTH {64} \ - ] $axis_pwm_0 - - # Create instance: clk_mux_0, and set properties - set clk_mux_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:clk_mux:1.0 clk_mux_0 ] - - # Create instance: clk_wiz_0, and set properties - set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:5.4 clk_wiz_0 ] - set_property -dict [ list \ -CONFIG.CLKOUT1_JITTER {236.910} \ -CONFIG.CLKOUT1_PHASE_ERROR {732.678} \ -CONFIG.CLKOUT1_REQUESTED_DUTY_CYCLE {50.0} \ -CONFIG.MMCM_BANDWIDTH {LOW} \ -CONFIG.MMCM_CLKFBOUT_MULT_F {21.000} \ -CONFIG.MMCM_CLKOUT0_DIVIDE_F {7.000} \ -CONFIG.MMCM_DIVCLK_DIVIDE {3} \ -CONFIG.USE_LOCKED {false} \ -CONFIG.USE_RESET {false} \ -CONFIG.USE_SPREAD_SPECTRUM {true} \ - ] $clk_wiz_0 - - # Create instance: proc_sys_reset_0, and set properties - set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ] - - # Create instance: proc_sys_reset_1, and set properties - set proc_sys_reset_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_1 ] - - # Create instance: processing_system7_0, and set properties - set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ] - set_property -dict [ list \ -CONFIG.PCW_ACT_APU_PERIPHERAL_FREQMHZ {650.000000} \ -CONFIG.PCW_ACT_DCI_PERIPHERAL_FREQMHZ {10.096154} \ -CONFIG.PCW_ACT_ENET0_PERIPHERAL_FREQMHZ {125.000000} \ -CONFIG.PCW_ACT_FPGA0_PERIPHERAL_FREQMHZ {100.000000} \ -CONFIG.PCW_ACT_FPGA1_PERIPHERAL_FREQMHZ {20.000000} \ -CONFIG.PCW_ACT_QSPI_PERIPHERAL_FREQMHZ {200.000000} \ -CONFIG.PCW_ACT_SDIO_PERIPHERAL_FREQMHZ {50.000000} \ -CONFIG.PCW_ACT_TTC0_CLK0_PERIPHERAL_FREQMHZ {108.333336} \ -CONFIG.PCW_ACT_TTC0_CLK1_PERIPHERAL_FREQMHZ {108.333336} \ -CONFIG.PCW_ACT_TTC0_CLK2_PERIPHERAL_FREQMHZ {108.333336} \ -CONFIG.PCW_ACT_TTC1_CLK0_PERIPHERAL_FREQMHZ {108.333336} \ -CONFIG.PCW_ACT_TTC1_CLK1_PERIPHERAL_FREQMHZ {108.333336} \ -CONFIG.PCW_ACT_TTC1_CLK2_PERIPHERAL_FREQMHZ {108.333336} \ -CONFIG.PCW_ACT_UART_PERIPHERAL_FREQMHZ {100.000000} \ -CONFIG.PCW_ACT_WDT_PERIPHERAL_FREQMHZ {108.333336} \ -CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {650} \ -CONFIG.PCW_ARMPLL_CTRL_FBDIV {26} \ -CONFIG.PCW_CLK0_FREQ {100000000} \ -CONFIG.PCW_CLK1_FREQ {20000000} \ -CONFIG.PCW_CPU_CPU_PLL_FREQMHZ {1300.000} \ -CONFIG.PCW_CRYSTAL_PERIPHERAL_FREQMHZ {50} \ -CONFIG.PCW_DCI_PERIPHERAL_DIVISOR0 {52} \ -CONFIG.PCW_DCI_PERIPHERAL_DIVISOR1 {2} \ -CONFIG.PCW_DDRPLL_CTRL_FBDIV {21} \ -CONFIG.PCW_DDR_DDR_PLL_FREQMHZ {1050.000} \ -CONFIG.PCW_ENET0_ENET0_IO {MIO 16 .. 27} \ -CONFIG.PCW_ENET0_GRP_MDIO_ENABLE {1} \ -CONFIG.PCW_ENET0_GRP_MDIO_IO {MIO 52 .. 53} \ -CONFIG.PCW_ENET0_PERIPHERAL_DIVISOR0 {8} \ -CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {1} \ -CONFIG.PCW_ENET0_RESET_ENABLE {1} \ -CONFIG.PCW_ENET0_RESET_IO {MIO 9} \ -CONFIG.PCW_ENET_RESET_ENABLE {1} \ -CONFIG.PCW_ENET_RESET_SELECT {Share reset pin} \ -CONFIG.PCW_EN_CLK1_PORT {1} \ -CONFIG.PCW_EN_EMIO_GPIO {1} \ -CONFIG.PCW_EN_ENET0 {1} \ -CONFIG.PCW_EN_GPIO {1} \ -CONFIG.PCW_EN_QSPI {1} \ -CONFIG.PCW_EN_SDIO0 {1} \ -CONFIG.PCW_EN_UART0 {1} \ -CONFIG.PCW_EN_UART1 {1} \ -CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR0 {5} \ -CONFIG.PCW_FCLK0_PERIPHERAL_DIVISOR1 {2} \ -CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR0 {10} \ -CONFIG.PCW_FCLK1_PERIPHERAL_DIVISOR1 {5} \ -CONFIG.PCW_FCLK_CLK1_BUF {TRUE} \ -CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100} \ -CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {20} \ -CONFIG.PCW_FPGA_FCLK1_ENABLE {1} \ -CONFIG.PCW_FTM_CTI_IN0 {} \ -CONFIG.PCW_FTM_CTI_IN2 {} \ -CONFIG.PCW_FTM_CTI_OUT0 {} \ -CONFIG.PCW_FTM_CTI_OUT2 {} \ -CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1} \ -CONFIG.PCW_GPIO_EMIO_GPIO_IO {2} \ -CONFIG.PCW_GPIO_EMIO_GPIO_WIDTH {2} \ -CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \ -CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \ -CONFIG.PCW_I2C_RESET_ENABLE {1} \ -CONFIG.PCW_IOPLL_CTRL_FBDIV {20} \ -CONFIG.PCW_IO_IO_PLL_FREQMHZ {1000.000} \ -CONFIG.PCW_MIO_0_DIRECTION {inout} \ -CONFIG.PCW_MIO_0_IOTYPE {LVCMOS 3.3V} \ -CONFIG.PCW_MIO_0_PULLUP {enabled} \ -CONFIG.PCW_MIO_0_SLEW {slow} \ -CONFIG.PCW_MIO_10_DIRECTION {inout} \ -CONFIG.PCW_MIO_10_IOTYPE {LVCMOS 3.3V} \ -CONFIG.PCW_MIO_10_PULLUP {enabled} \ -CONFIG.PCW_MIO_10_SLEW {slow} \ -CONFIG.PCW_MIO_11_DIRECTION {inout} \ -CONFIG.PCW_MIO_11_IOTYPE {LVCMOS 3.3V} \ -CONFIG.PCW_MIO_11_PULLUP {enabled} \ -CONFIG.PCW_MIO_11_SLEW {slow} \ -CONFIG.PCW_MIO_12_DIRECTION {inout} \ -CONFIG.PCW_MIO_12_IOTYPE {LVCMOS 3.3V} \ -CONFIG.PCW_MIO_12_PULLUP {enabled} \ -CONFIG.PCW_MIO_12_SLEW {slow} \ -CONFIG.PCW_MIO_13_DIRECTION {inout} \ -CONFIG.PCW_MIO_13_IOTYPE {LVCMOS 3.3V} \ -CONFIG.PCW_MIO_13_PULLUP {enabled} \ -CONFIG.PCW_MIO_13_SLEW {slow} \ -CONFIG.PCW_MIO_14_DIRECTION {in} \ -CONFIG.PCW_MIO_14_IOTYPE {LVCMOS 3.3V} \ -CONFIG.PCW_MIO_14_PULLUP {enabled} \ -CONFIG.PCW_MIO_14_SLEW {slow} \ -CONFIG.PCW_MIO_15_DIRECTION {out} \ -CONFIG.PCW_MIO_15_IOTYPE {LVCMOS 3.3V} \ -CONFIG.PCW_MIO_15_PULLUP {enabled} \ -CONFIG.PCW_MIO_15_SLEW {slow} \ -CONFIG.PCW_MIO_16_DIRECTION {out} \ -CONFIG.PCW_MIO_16_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_16_PULLUP {enabled} \ -CONFIG.PCW_MIO_16_SLEW {slow} \ -CONFIG.PCW_MIO_17_DIRECTION {out} \ -CONFIG.PCW_MIO_17_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_17_PULLUP {enabled} \ -CONFIG.PCW_MIO_17_SLEW {slow} \ -CONFIG.PCW_MIO_18_DIRECTION {out} \ -CONFIG.PCW_MIO_18_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_18_PULLUP {enabled} \ -CONFIG.PCW_MIO_18_SLEW {slow} \ -CONFIG.PCW_MIO_19_DIRECTION {out} \ -CONFIG.PCW_MIO_19_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_19_PULLUP {enabled} \ -CONFIG.PCW_MIO_19_SLEW {slow} \ -CONFIG.PCW_MIO_1_DIRECTION {out} \ -CONFIG.PCW_MIO_1_IOTYPE {LVCMOS 3.3V} \ -CONFIG.PCW_MIO_1_PULLUP {enabled} \ -CONFIG.PCW_MIO_1_SLEW {slow} \ -CONFIG.PCW_MIO_20_DIRECTION {out} \ -CONFIG.PCW_MIO_20_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_20_PULLUP {enabled} \ -CONFIG.PCW_MIO_20_SLEW {slow} \ -CONFIG.PCW_MIO_21_DIRECTION {out} \ -CONFIG.PCW_MIO_21_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_21_PULLUP {enabled} \ -CONFIG.PCW_MIO_21_SLEW {slow} \ -CONFIG.PCW_MIO_22_DIRECTION {in} \ -CONFIG.PCW_MIO_22_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_22_PULLUP {enabled} \ -CONFIG.PCW_MIO_22_SLEW {slow} \ -CONFIG.PCW_MIO_23_DIRECTION {in} \ -CONFIG.PCW_MIO_23_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_23_PULLUP {enabled} \ -CONFIG.PCW_MIO_23_SLEW {slow} \ -CONFIG.PCW_MIO_24_DIRECTION {in} \ -CONFIG.PCW_MIO_24_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_24_PULLUP {enabled} \ -CONFIG.PCW_MIO_24_SLEW {slow} \ -CONFIG.PCW_MIO_25_DIRECTION {in} \ -CONFIG.PCW_MIO_25_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_25_PULLUP {enabled} \ -CONFIG.PCW_MIO_25_SLEW {slow} \ -CONFIG.PCW_MIO_26_DIRECTION {in} \ -CONFIG.PCW_MIO_26_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_26_PULLUP {enabled} \ -CONFIG.PCW_MIO_26_SLEW {slow} \ -CONFIG.PCW_MIO_27_DIRECTION {in} \ -CONFIG.PCW_MIO_27_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_27_PULLUP {enabled} \ -CONFIG.PCW_MIO_27_SLEW {slow} \ -CONFIG.PCW_MIO_28_DIRECTION {inout} \ -CONFIG.PCW_MIO_28_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_28_PULLUP {enabled} \ -CONFIG.PCW_MIO_28_SLEW {slow} \ -CONFIG.PCW_MIO_29_DIRECTION {inout} \ -CONFIG.PCW_MIO_29_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_29_PULLUP {enabled} \ -CONFIG.PCW_MIO_29_SLEW {slow} \ -CONFIG.PCW_MIO_2_DIRECTION {inout} \ -CONFIG.PCW_MIO_2_IOTYPE {LVCMOS 3.3V} \ -CONFIG.PCW_MIO_2_PULLUP {disabled} \ -CONFIG.PCW_MIO_2_SLEW {slow} \ -CONFIG.PCW_MIO_30_DIRECTION {inout} \ -CONFIG.PCW_MIO_30_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_30_PULLUP {enabled} \ -CONFIG.PCW_MIO_30_SLEW {slow} \ -CONFIG.PCW_MIO_31_DIRECTION {inout} \ -CONFIG.PCW_MIO_31_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_31_PULLUP {enabled} \ -CONFIG.PCW_MIO_31_SLEW {slow} \ -CONFIG.PCW_MIO_32_DIRECTION {inout} \ -CONFIG.PCW_MIO_32_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_32_PULLUP {enabled} \ -CONFIG.PCW_MIO_32_SLEW {slow} \ -CONFIG.PCW_MIO_33_DIRECTION {inout} \ -CONFIG.PCW_MIO_33_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_33_PULLUP {enabled} \ -CONFIG.PCW_MIO_33_SLEW {slow} \ -CONFIG.PCW_MIO_34_DIRECTION {inout} \ -CONFIG.PCW_MIO_34_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_34_PULLUP {enabled} \ -CONFIG.PCW_MIO_34_SLEW {slow} \ -CONFIG.PCW_MIO_35_DIRECTION {inout} \ -CONFIG.PCW_MIO_35_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_35_PULLUP {enabled} \ -CONFIG.PCW_MIO_35_SLEW {slow} \ -CONFIG.PCW_MIO_36_DIRECTION {inout} \ -CONFIG.PCW_MIO_36_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_36_PULLUP {enabled} \ -CONFIG.PCW_MIO_36_SLEW {slow} \ -CONFIG.PCW_MIO_37_DIRECTION {inout} \ -CONFIG.PCW_MIO_37_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_37_PULLUP {enabled} \ -CONFIG.PCW_MIO_37_SLEW {slow} \ -CONFIG.PCW_MIO_38_DIRECTION {inout} \ -CONFIG.PCW_MIO_38_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_38_PULLUP {enabled} \ -CONFIG.PCW_MIO_38_SLEW {slow} \ -CONFIG.PCW_MIO_39_DIRECTION {inout} \ -CONFIG.PCW_MIO_39_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_39_PULLUP {enabled} \ -CONFIG.PCW_MIO_39_SLEW {slow} \ -CONFIG.PCW_MIO_3_DIRECTION {inout} \ -CONFIG.PCW_MIO_3_IOTYPE {LVCMOS 3.3V} \ -CONFIG.PCW_MIO_3_PULLUP {disabled} \ -CONFIG.PCW_MIO_3_SLEW {slow} \ -CONFIG.PCW_MIO_40_DIRECTION {inout} \ -CONFIG.PCW_MIO_40_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_40_PULLUP {enabled} \ -CONFIG.PCW_MIO_40_SLEW {slow} \ -CONFIG.PCW_MIO_41_DIRECTION {inout} \ -CONFIG.PCW_MIO_41_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_41_PULLUP {enabled} \ -CONFIG.PCW_MIO_41_SLEW {slow} \ -CONFIG.PCW_MIO_42_DIRECTION {inout} \ -CONFIG.PCW_MIO_42_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_42_PULLUP {enabled} \ -CONFIG.PCW_MIO_42_SLEW {slow} \ -CONFIG.PCW_MIO_43_DIRECTION {inout} \ -CONFIG.PCW_MIO_43_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_43_PULLUP {enabled} \ -CONFIG.PCW_MIO_43_SLEW {slow} \ -CONFIG.PCW_MIO_44_DIRECTION {inout} \ -CONFIG.PCW_MIO_44_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_44_PULLUP {enabled} \ -CONFIG.PCW_MIO_44_SLEW {slow} \ -CONFIG.PCW_MIO_45_DIRECTION {inout} \ -CONFIG.PCW_MIO_45_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_45_PULLUP {enabled} \ -CONFIG.PCW_MIO_45_SLEW {slow} \ -CONFIG.PCW_MIO_46_DIRECTION {inout} \ -CONFIG.PCW_MIO_46_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_46_PULLUP {enabled} \ -CONFIG.PCW_MIO_46_SLEW {slow} \ -CONFIG.PCW_MIO_47_DIRECTION {in} \ -CONFIG.PCW_MIO_47_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_47_PULLUP {enabled} \ -CONFIG.PCW_MIO_47_SLEW {slow} \ -CONFIG.PCW_MIO_48_DIRECTION {out} \ -CONFIG.PCW_MIO_48_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_48_PULLUP {enabled} \ -CONFIG.PCW_MIO_48_SLEW {slow} \ -CONFIG.PCW_MIO_49_DIRECTION {in} \ -CONFIG.PCW_MIO_49_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_49_PULLUP {enabled} \ -CONFIG.PCW_MIO_49_SLEW {slow} \ -CONFIG.PCW_MIO_4_DIRECTION {inout} \ -CONFIG.PCW_MIO_4_IOTYPE {LVCMOS 3.3V} \ -CONFIG.PCW_MIO_4_PULLUP {disabled} \ -CONFIG.PCW_MIO_4_SLEW {slow} \ -CONFIG.PCW_MIO_50_DIRECTION {inout} \ -CONFIG.PCW_MIO_50_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_50_PULLUP {enabled} \ -CONFIG.PCW_MIO_50_SLEW {slow} \ -CONFIG.PCW_MIO_51_DIRECTION {inout} \ -CONFIG.PCW_MIO_51_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_51_PULLUP {enabled} \ -CONFIG.PCW_MIO_51_SLEW {slow} \ -CONFIG.PCW_MIO_52_DIRECTION {out} \ -CONFIG.PCW_MIO_52_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_52_PULLUP {enabled} \ -CONFIG.PCW_MIO_52_SLEW {slow} \ -CONFIG.PCW_MIO_53_DIRECTION {inout} \ -CONFIG.PCW_MIO_53_IOTYPE {LVCMOS 1.8V} \ -CONFIG.PCW_MIO_53_PULLUP {enabled} \ -CONFIG.PCW_MIO_53_SLEW {slow} \ -CONFIG.PCW_MIO_5_DIRECTION {inout} \ -CONFIG.PCW_MIO_5_IOTYPE {LVCMOS 3.3V} \ -CONFIG.PCW_MIO_5_PULLUP {disabled} \ -CONFIG.PCW_MIO_5_SLEW {slow} \ -CONFIG.PCW_MIO_6_DIRECTION {out} \ -CONFIG.PCW_MIO_6_IOTYPE {LVCMOS 3.3V} \ -CONFIG.PCW_MIO_6_PULLUP {disabled} \ -CONFIG.PCW_MIO_6_SLEW {slow} \ -CONFIG.PCW_MIO_7_DIRECTION {out} \ -CONFIG.PCW_MIO_7_IOTYPE {LVCMOS 3.3V} \ -CONFIG.PCW_MIO_7_PULLUP {disabled} \ -CONFIG.PCW_MIO_7_SLEW {slow} \ -CONFIG.PCW_MIO_8_DIRECTION {out} \ -CONFIG.PCW_MIO_8_IOTYPE {LVCMOS 3.3V} \ -CONFIG.PCW_MIO_8_PULLUP {disabled} \ -CONFIG.PCW_MIO_8_SLEW {slow} \ -CONFIG.PCW_MIO_9_DIRECTION {out} \ -CONFIG.PCW_MIO_9_IOTYPE {LVCMOS 3.3V} \ -CONFIG.PCW_MIO_9_PULLUP {enabled} \ -CONFIG.PCW_MIO_9_SLEW {slow} \ -CONFIG.PCW_MIO_TREE_PERIPHERALS {GPIO#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#Quad SPI Flash#GPIO#Quad SPI Flash#ENET Reset#GPIO#GPIO#GPIO#GPIO#UART 0#UART 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#Enet 0#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#GPIO#SD 0#SD 0#SD 0#SD 0#SD 0#SD 0#GPIO#SD 0#UART 1#UART 1#GPIO#GPIO#Enet 0#Enet 0} \ -CONFIG.PCW_MIO_TREE_SIGNALS {gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]#qspi0_sclk#gpio[7]#qspi_fbclk#reset#gpio[10]#gpio[11]#gpio[12]#gpio[13]#rx#tx#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#gpio[28]#gpio[29]#gpio[30]#gpio[31]#gpio[32]#gpio[33]#gpio[34]#gpio[35]#gpio[36]#gpio[37]#gpio[38]#gpio[39]#clk#cmd#data[0]#data[1]#data[2]#data[3]#gpio[46]#cd#tx#rx#gpio[50]#gpio[51]#mdc#mdio} \ -CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY0 {0.223} \ -CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY1 {0.212} \ -CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY2 {0.085} \ -CONFIG.PCW_PACKAGE_DDR_BOARD_DELAY3 {0.092} \ -CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_0 {0.040} \ -CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_1 {0.058} \ -CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_2 {-0.009} \ -CONFIG.PCW_PACKAGE_DDR_DQS_TO_CLK_DELAY_3 {-0.033} \ -CONFIG.PCW_PCAP_PERIPHERAL_DIVISOR0 {5} \ -CONFIG.PCW_PERIPHERAL_BOARD_PRESET {part0} \ -CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \ -CONFIG.PCW_QSPI_GRP_FBCLK_ENABLE {1} \ -CONFIG.PCW_QSPI_GRP_FBCLK_IO {MIO 8} \ -CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \ -CONFIG.PCW_QSPI_GRP_SINGLE_SS_IO {MIO 1 .. 6} \ -CONFIG.PCW_QSPI_PERIPHERAL_DIVISOR0 {5} \ -CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \ -CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \ -CONFIG.PCW_SD0_GRP_CD_ENABLE {1} \ -CONFIG.PCW_SD0_GRP_CD_IO {MIO 47} \ -CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \ -CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45} \ -CONFIG.PCW_SDIO_PERIPHERAL_DIVISOR0 {20} \ -CONFIG.PCW_SDIO_PERIPHERAL_FREQMHZ {50} \ -CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \ -CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} \ -CONFIG.PCW_UART0_UART0_IO {MIO 14 .. 15} \ -CONFIG.PCW_UART1_PERIPHERAL_ENABLE {1} \ -CONFIG.PCW_UART1_UART1_IO {MIO 48 .. 49} \ -CONFIG.PCW_UART_PERIPHERAL_DIVISOR0 {10} \ -CONFIG.PCW_UART_PERIPHERAL_VALID {1} \ -CONFIG.PCW_UIPARAM_ACT_DDR_FREQ_MHZ {525.000000} \ -CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.223} \ -CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.212} \ -CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.085} \ -CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.092} \ -CONFIG.PCW_UIPARAM_DDR_BUS_WIDTH {16 Bit} \ -CONFIG.PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM {25.8} \ -CONFIG.PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH {80.4535} \ -CONFIG.PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM {25.8} \ -CONFIG.PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH {80.4535} \ -CONFIG.PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH {80.4535} \ -CONFIG.PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH {80.4535} \ -CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {4096 MBits} \ -CONFIG.PCW_UIPARAM_DDR_DQS_0_LENGTH_MM {15.6} \ -CONFIG.PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH {105.056} \ -CONFIG.PCW_UIPARAM_DDR_DQS_1_LENGTH_MM {18.8} \ -CONFIG.PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH {66.904} \ -CONFIG.PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH {89.1715} \ -CONFIG.PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH {113.63} \ -CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.040} \ -CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.058} \ -CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {0.0} \ -CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {0.0} \ -CONFIG.PCW_UIPARAM_DDR_DQ_0_LENGTH_MM {16.5} \ -CONFIG.PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH {98.503} \ -CONFIG.PCW_UIPARAM_DDR_DQ_1_LENGTH_MM {18} \ -CONFIG.PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH {68.5855} \ -CONFIG.PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH {90.295} \ -CONFIG.PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH {103.977} \ -CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {16 Bits} \ -CONFIG.PCW_UIPARAM_DDR_FREQ_MHZ {525} \ -CONFIG.PCW_UIPARAM_DDR_PARTNO {MT41J256M16 RE-125} \ -CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {15} \ -CONFIG.PCW_UIPARAM_DDR_T_FAW {40.0} \ -CONFIG.PCW_UIPARAM_DDR_T_RC {48.91} \ -CONFIG.PCW_USB_RESET_ENABLE {1} \ -CONFIG.PCW_USE_M_AXI_GP0 {1} \ -CONFIG.PCW_USE_S_AXI_GP0 {0} \ -CONFIG.PCW_USE_S_AXI_HP0 {1} \ - ] $processing_system7_0 - - # Create instance: ps7_0_axi_periph, and set properties - set ps7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps7_0_axi_periph ] - set_property -dict [ list \ -CONFIG.NUM_MI {2} \ - ] $ps7_0_axi_periph - - # Create instance: rpm_check_0, and set properties - set rpm_check_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:rpm_check:1.0 rpm_check_0 ] - - # Create instance: rx_fifo, and set properties - set rx_fifo [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:1.1 rx_fifo ] - set_property -dict [ list \ -CONFIG.FIFO_DEPTH {512} \ -CONFIG.TDATA_NUM_BYTES {8} \ - ] $rx_fifo - - # Create instance: tx_fifo, and set properties - set tx_fifo [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:1.1 tx_fifo ] - set_property -dict [ list \ -CONFIG.FIFO_DEPTH {512} \ -CONFIG.TDATA_NUM_BYTES {8} \ - ] $tx_fifo - - # Create instance: xlconcat_0, and set properties - set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ] - set_property -dict [ list \ -CONFIG.NUM_PORTS {4} \ - ] $xlconcat_0 - - # Create instance: xlconcat_1, and set properties - set xlconcat_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_1 ] - set_property -dict [ list \ -CONFIG.IN0_WIDTH {4} \ -CONFIG.IN1_WIDTH {28} \ - ] $xlconcat_1 - - # Create instance: xlconstant_0, and set properties - set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] - set_property -dict [ list \ -CONFIG.CONST_VAL {0} \ -CONFIG.CONST_WIDTH {28} \ - ] $xlconstant_0 - - # Create instance: xlslice_0, and set properties - set xlslice_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0 ] - - # Create instance: xlslice_1, and set properties - set xlslice_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_1 ] - set_property -dict [ list \ -CONFIG.DIN_FROM {3} \ -CONFIG.DOUT_WIDTH {4} \ - ] $xlslice_1 - - # Create instance: xlslice_2, and set properties - set xlslice_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_2 ] - set_property -dict [ list \ -CONFIG.DIN_FROM {15} \ -CONFIG.DOUT_WIDTH {16} \ - ] $xlslice_2 - - # Create instance: xlslice_3, and set properties - set xlslice_3 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_3 ] - set_property -dict [ list \ -CONFIG.DIN_FROM {19} \ -CONFIG.DIN_TO {4} \ -CONFIG.DOUT_WIDTH {16} \ - ] $xlslice_3 - - # Create instance: xlslice_4, and set properties - set xlslice_4 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_4 ] - set_property -dict [ list \ -CONFIG.DIN_FROM {20} \ -CONFIG.DIN_TO {20} \ -CONFIG.DOUT_WIDTH {1} \ - ] $xlslice_4 - - # Create instance: xlslice_5, and set properties - set xlslice_5 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_5 ] - set_property -dict [ list \ -CONFIG.DIN_FROM {21} \ -CONFIG.DIN_TO {21} \ -CONFIG.DOUT_WIDTH {1} \ - ] $xlslice_5 - - # Create instance: zero_16, and set properties - set zero_16 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 zero_16 ] - set_property -dict [ list \ -CONFIG.CONST_VAL {0} \ -CONFIG.CONST_WIDTH {16} \ - ] $zero_16 - - # Create interface connections - connect_bd_intf_net -intf_net AXI_StreamCapture_0_m_axis_s2mm [get_bd_intf_pins AXI_StreamCapture_0/m_axis_s2mm] [get_bd_intf_pins axi_datamover_0/S_AXIS_S2MM] - connect_bd_intf_net -intf_net AXI_StreamCapture_0_m_axis_s2mm_cmd [get_bd_intf_pins AXI_StreamCapture_0/m_axis_s2mm_cmd] [get_bd_intf_pins axi_datamover_0/S_AXIS_S2MM_CMD] - connect_bd_intf_net -intf_net Angle_RPM_Ib_Ia_m_axis [get_bd_intf_pins Angle_RPM_Ib_Ia/m_axis] [get_bd_intf_pins rx_fifo/S_AXIS] -connect_bd_intf_net -intf_net [get_bd_intf_nets Angle_RPM_Ib_Ia_m_axis] [get_bd_intf_pins axis_monitor_1/s00_axis] [get_bd_intf_pins rx_fifo/S_AXIS] -connect_bd_intf_net -intf_net Conn [get_bd_intf_pins FOC/s_axis_V1] [get_bd_intf_pins axis_monitor_1/s01_axis] -connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins FOC/SLOT_0_AXIS] [get_bd_intf_pins axis_monitor_1/s02_axis] -connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins FOC/m_axis] [get_bd_intf_pins axis_monitor_1/s03_axis] -connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins FOC/s_axis_V2] [get_bd_intf_pins axis_monitor_1/s04_axis] -connect_bd_intf_net -intf_net Conn4 [get_bd_intf_pins FOC/SLOT_0_AXIS1] [get_bd_intf_pins axis_monitor_1/s05_axis] - connect_bd_intf_net -intf_net FOC_m_axis_V [get_bd_intf_pins FOC/m_axis_V] [get_bd_intf_pins tx_fifo/S_AXIS] -connect_bd_intf_net -intf_net [get_bd_intf_nets FOC_m_axis_V] [get_bd_intf_pins axis_monitor_1/s06_axis] [get_bd_intf_pins tx_fifo/S_AXIS] - connect_bd_intf_net -intf_net axi_datamover_0_M_AXIS_S2MM_STS [get_bd_intf_pins AXI_StreamCapture_0/s_axis_s2mm_sts] [get_bd_intf_pins axi_datamover_0/M_AXIS_S2MM_STS] - connect_bd_intf_net -intf_net axi_datamover_0_M_AXI_S2MM [get_bd_intf_pins axi_datamover_0/M_AXI_S2MM] [get_bd_intf_pins axi_interconnect_0/S00_AXI] - connect_bd_intf_net -intf_net axi_interconnect_0_M00_AXI [get_bd_intf_pins axi_interconnect_0/M00_AXI] [get_bd_intf_pins processing_system7_0/S_AXI_HP0] - connect_bd_intf_net -intf_net axis_AD7403_0_m_axis [get_bd_intf_pins axis_AD7403_0/m_axis] [get_bd_intf_pins axis_data_fifo_1/S_AXIS] - connect_bd_intf_net -intf_net axis_data_fifo_0_M_AXIS [get_bd_intf_pins AXI_StreamCapture_0/s_axis] [get_bd_intf_pins axis_data_fifo_0/M_AXIS] - connect_bd_intf_net -intf_net axis_data_fifo_1_M_AXIS [get_bd_intf_pins Ib_Ia/S_AXIS] [get_bd_intf_pins axis_data_fifo_1/M_AXIS] - connect_bd_intf_net -intf_net axis_decimate_0_m_axis [get_bd_intf_pins axis_data_fifo_0/S_AXIS] [get_bd_intf_pins axis_decimate_0/m_axis] - connect_bd_intf_net -intf_net axis_encoder_0_m_angle [get_bd_intf_pins Angle_RPM_Ib_Ia/sc_axis] [get_bd_intf_pins axis_encoder_0/m_angle] - connect_bd_intf_net -intf_net axis_encoder_0_m_rpm [get_bd_intf_pins Angle_RPM_Ib_Ia/sb_axis] [get_bd_intf_pins axis_encoder_0/m_rpm] - connect_bd_intf_net -intf_net axis_monitor_1_m_axis [get_bd_intf_pins axis_decimate_0/s_axis] [get_bd_intf_pins axis_monitor_1/m_axis] - connect_bd_intf_net -intf_net axis_subset_converter_0_M_AXIS [get_bd_intf_pins Angle_RPM_Ib_Ia/sa_axis] [get_bd_intf_pins Ib_Ia/M_AXIS] - connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR] - connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO] - connect_bd_intf_net -intf_net processing_system7_0_M_AXI_GP0 [get_bd_intf_pins processing_system7_0/M_AXI_GP0] [get_bd_intf_pins ps7_0_axi_periph/S00_AXI] - connect_bd_intf_net -intf_net ps7_0_axi_periph_M00_AXI [get_bd_intf_pins axi_reg32_0/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M00_AXI] - connect_bd_intf_net -intf_net ps7_0_axi_periph_M01_AXI [get_bd_intf_pins AXI_StreamCapture_0/S_AXI] [get_bd_intf_pins ps7_0_axi_periph/M01_AXI] - connect_bd_intf_net -intf_net rx_fifo_M_AXIS [get_bd_intf_pins FOC/s_axis_V] [get_bd_intf_pins rx_fifo/M_AXIS] - connect_bd_intf_net -intf_net tx_fifo_M_AXIS [get_bd_intf_pins axis_pwm_0/S_AXIS] [get_bd_intf_pins tx_fifo/M_AXIS] - - # Create port connections - connect_bd_net -net A_1 [get_bd_ports ENC_A] [get_bd_pins axis_encoder_0/A] - connect_bd_net -net Angle_Shift_slice_Dout [get_bd_pins Angle_Shift_slice/Dout] [get_bd_pins axis_encoder_0/angle_shift] - connect_bd_net -net BTN0_1 [get_bd_ports BTN0] [get_bd_pins rpm_check_0/button] - connect_bd_net -net B_1 [get_bd_ports ENC_B] [get_bd_pins axis_encoder_0/B] - connect_bd_net -net FOC_Id_out [get_bd_pins FOC/Id_out] [get_bd_pins axi_reg32_0/RR2] - connect_bd_net -net FOC_Iq_out [get_bd_pins FOC/Iq_out] [get_bd_pins axi_reg32_0/RR3] - connect_bd_net -net FOC_dout [get_bd_pins FOC/RPM] [get_bd_pins axi_reg32_0/RR1] [get_bd_pins xlslice_2/Din] - connect_bd_net -net I_1 [get_bd_ports ENC_I] [get_bd_pins axis_encoder_0/I] - connect_bd_net -net SDI1_1 [get_bd_ports SDI1] [get_bd_pins xlconcat_0/In0] - connect_bd_net -net SDI2_1 [get_bd_ports SDI2] [get_bd_pins xlconcat_0/In1] - connect_bd_net -net SDI3_1 [get_bd_ports SDI3] [get_bd_pins xlconcat_0/In2] - connect_bd_net -net SDV_1 [get_bd_ports SDV] [get_bd_pins xlconcat_0/In3] - connect_bd_net -net SW0_1 [get_bd_ports SW0] [get_bd_pins clk_mux_0/sel] [get_bd_pins rpm_check_0/ss_in] - connect_bd_net -net Vq_1 [get_bd_pins FOC/Vq] [get_bd_pins axi_reg32_0/WR12] - connect_bd_net -net axi_reg32_0_WR0 [get_bd_pins FOC/control] [get_bd_pins axi_reg32_0/WR0] [get_bd_pins rpm_check_0/mode_in] - connect_bd_net -net axi_reg32_0_WR1 [get_bd_pins FOC/Flux_Sp] [get_bd_pins axi_reg32_0/WR1] - connect_bd_net -net axi_reg32_0_WR2 [get_bd_pins FOC/Flux_Kp] [get_bd_pins axi_reg32_0/WR2] - connect_bd_net -net axi_reg32_0_WR3 [get_bd_pins FOC/Flux_Ki] [get_bd_pins axi_reg32_0/WR3] - connect_bd_net -net axi_reg32_0_WR4 [get_bd_pins FOC/Torque_Sp] [get_bd_pins axi_reg32_0/WR4] - connect_bd_net -net axi_reg32_0_WR5 [get_bd_pins FOC/Torque_Kp] [get_bd_pins axi_reg32_0/WR5] - connect_bd_net -net axi_reg32_0_WR6 [get_bd_pins FOC/Torque_Ki] [get_bd_pins axi_reg32_0/WR6] - connect_bd_net -net axi_reg32_0_WR7 [get_bd_pins FOC/RPM_Sp] [get_bd_pins axi_reg32_0/WR7] - connect_bd_net -net axi_reg32_0_WR8 [get_bd_pins FOC/RPM_Kp] [get_bd_pins axi_reg32_0/WR8] - connect_bd_net -net axi_reg32_0_WR9 [get_bd_pins FOC/RPM_Ki] [get_bd_pins axi_reg32_0/WR9] - connect_bd_net -net axi_reg32_0_WR10 [get_bd_pins Angle_Shift_slice/Din] [get_bd_pins axi_reg32_0/WR10] - connect_bd_net -net axi_reg32_0_WR11 [get_bd_pins FOC/Vd] [get_bd_pins axi_reg32_0/WR11] - connect_bd_net -net axi_reg32_0_WR13 [get_bd_pins axi_reg32_0/WR13] [get_bd_pins axis_decimate_0/decimation] - connect_bd_net -net axi_reg32_0_WR14 [get_bd_pins axi_reg32_0/WR14] [get_bd_pins xlslice_0/Din] - connect_bd_net -net axi_reg32_0_WR15 [get_bd_pins axi_reg32_0/WR15] [get_bd_pins xlslice_1/Din] [get_bd_pins xlslice_3/Din] [get_bd_pins xlslice_4/Din] [get_bd_pins xlslice_5/Din] - connect_bd_net -net axis_AD7403_0_clkout [get_bd_ports SCLK] [get_bd_pins axis_AD7403_0/clkout] - connect_bd_net -net axis_encoder_0_angle_data [get_bd_pins Angle_concat/In0] [get_bd_pins axis_encoder_0/angle_data] - connect_bd_net -net axis_pwm_0_pwm_h [get_bd_ports GH] [get_bd_pins axis_pwm_0/pwm_h] - connect_bd_net -net axis_pwm_0_pwm_l [get_bd_ports GL] [get_bd_pins axis_pwm_0/pwm_l] - connect_bd_net -net clk_mux_0_clkout [get_bd_pins axis_AD7403_0/m_axis_aclk] [get_bd_pins axis_data_fifo_1/s_axis_aclk] [get_bd_pins clk_mux_0/clkout] [get_bd_pins proc_sys_reset_1/slowest_sync_clk] - connect_bd_net -net clk_wiz_0_clk_out1 [get_bd_pins clk_mux_0/clk1] [get_bd_pins clk_wiz_0/clk_out1] - connect_bd_net -net proc_sys_reset_0_interconnect_aresetn [get_bd_pins axi_interconnect_0/ARESETN] [get_bd_pins proc_sys_reset_0/interconnect_aresetn] [get_bd_pins ps7_0_axi_periph/ARESETN] - connect_bd_net -net proc_sys_reset_0_peripheral_aresetn [get_bd_pins AXI_StreamCapture_0/axi_aresetn] [get_bd_pins Angle_RPM_Ib_Ia/s_axis_aresetn] [get_bd_pins FOC/ap_rst_n] [get_bd_pins Ib_Ia/aresetn] [get_bd_pins axi_datamover_0/m_axi_s2mm_aresetn] [get_bd_pins axi_datamover_0/m_axis_s2mm_cmdsts_aresetn] [get_bd_pins axi_interconnect_0/M00_ARESETN] [get_bd_pins axi_interconnect_0/S00_ARESETN] [get_bd_pins axi_reg32_0/s_axi_aresetn] [get_bd_pins axis_data_fifo_0/s_axis_aresetn] [get_bd_pins axis_data_fifo_1/m_axis_aresetn] [get_bd_pins axis_decimate_0/s_axis_aresetn] [get_bd_pins axis_encoder_0/axis_aresetn] [get_bd_pins axis_monitor_1/axis_aresetn] [get_bd_pins axis_pwm_0/s_axis_aresetn] [get_bd_pins proc_sys_reset_0/peripheral_aresetn] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/M01_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins rx_fifo/s_axis_aresetn] [get_bd_pins tx_fifo/s_axis_aresetn] - connect_bd_net -net proc_sys_reset_1_peripheral_aresetn [get_bd_pins axis_AD7403_0/m_axis_aresetn] [get_bd_pins axis_data_fifo_1/s_axis_aresetn] [get_bd_pins proc_sys_reset_1/peripheral_aresetn] - connect_bd_net -net processing_system7_0_FCLK_CLK1 [get_bd_pins AXI_StreamCapture_0/axi_aclk] [get_bd_pins Angle_RPM_Ib_Ia/s_axis_aclk] [get_bd_pins FOC/ap_clk] [get_bd_pins Ib_Ia/aclk] [get_bd_pins axi_datamover_0/m_axi_s2mm_aclk] [get_bd_pins axi_datamover_0/m_axis_s2mm_cmdsts_awclk] [get_bd_pins axi_interconnect_0/ACLK] [get_bd_pins axi_interconnect_0/M00_ACLK] [get_bd_pins axi_interconnect_0/S00_ACLK] [get_bd_pins axi_reg32_0/s_axi_aclk] [get_bd_pins axis_data_fifo_0/s_axis_aclk] [get_bd_pins axis_data_fifo_1/m_axis_aclk] [get_bd_pins axis_decimate_0/s_axis_aclk] [get_bd_pins axis_encoder_0/axis_aclk] [get_bd_pins axis_monitor_1/axis_aclk] [get_bd_pins axis_pwm_0/s_axis_aclk] [get_bd_pins clk_mux_0/clk0] [get_bd_pins clk_wiz_0/clk_in1] [get_bd_pins proc_sys_reset_0/slowest_sync_clk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/M01_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins rpm_check_0/aclk] [get_bd_pins rx_fifo/s_axis_aclk] [get_bd_pins tx_fifo/s_axis_aclk] - connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins proc_sys_reset_0/ext_reset_in] [get_bd_pins proc_sys_reset_1/ext_reset_in] [get_bd_pins processing_system7_0/FCLK_RESET0_N] - connect_bd_net -net rpm_check_0_led [get_bd_ports led] [get_bd_pins rpm_check_0/led] [get_bd_pins xlconcat_1/In0] - connect_bd_net -net xlconcat_0_dout [get_bd_pins axis_AD7403_0/din] [get_bd_pins xlconcat_0/dout] - connect_bd_net -net xlconcat_1_dout [get_bd_pins Angle_concat/dout] [get_bd_pins axi_reg32_0/RR0] - connect_bd_net -net xlconcat_1_dout1 [get_bd_pins axi_reg32_0/RR4] [get_bd_pins xlconcat_1/dout] - connect_bd_net -net xlconstant_0_dout [get_bd_pins xlconcat_1/In1] [get_bd_pins xlconstant_0/dout] - connect_bd_net -net xlslice_1_Dout [get_bd_pins axis_monitor_1/mux_in] [get_bd_pins xlslice_1/Dout] - connect_bd_net -net xlslice_2_Dout [get_bd_pins rpm_check_0/rpm_data] [get_bd_pins xlslice_2/Dout] - connect_bd_net -net xlslice_3_Dout [get_bd_pins rpm_check_0/tolerance_in] [get_bd_pins xlslice_3/Dout] - connect_bd_net -net xlslice_4_Dout [get_bd_pins rpm_check_0/led_in] [get_bd_pins xlslice_4/Dout] - connect_bd_net -net xlslice_5_Dout [get_bd_pins rpm_check_0/restart_in] [get_bd_pins xlslice_5/Dout] - connect_bd_net -net zero_16_dout [get_bd_pins Angle_concat/In1] [get_bd_pins zero_16/dout] - - # Create address segments - create_bd_addr_seg -range 0x20000000 -offset 0x00000000 [get_bd_addr_spaces axi_datamover_0/Data_S2MM] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_HP0_DDR_LOWOCM - create_bd_addr_seg -range 0x00010000 -offset 0x43C10000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs AXI_StreamCapture_0/S_AXI/S_AXI_reg] SEG_AXI_StreamCapture_0_S_AXI_reg - create_bd_addr_seg -range 0x00010000 -offset 0x43C00000 [get_bd_addr_spaces processing_system7_0/Data] [get_bd_addr_segs axi_reg32_0/S_AXI/S_AXI_reg] SEG_axi_reg32_0_S_AXI_reg - - - # Restore current instance - current_bd_instance $oldCurInst - - save_bd_design -} -# End of create_root_design() - - -################################################################## -# MAIN FLOW -################################################################## - -create_root_design "" - - diff --git a/boards/Ultra96/Readme.md b/boards/Ultra96/Readme.md deleted file mode 100644 index 1b101fb..0000000 --- a/boards/Ultra96/Readme.md +++ /dev/null @@ -1 +0,0 @@ -Board folder containing the files required for running SPYN on Ultra96 diff --git a/boards/Ultra96/__init__.py b/boards/Ultra96/__init__.py deleted file mode 100644 index e6fe05a..0000000 --- a/boards/Ultra96/__init__.py +++ /dev/null @@ -1,35 +0,0 @@ -# Copyright (c) 2018, Xilinx, Inc. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# 1. Redistributions of source code must retain the above copyright notice, -# this list of conditions and the following disclaimer. -# -# 2. Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# -# 3. Neither the name of the copyright holder nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, -# THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR -# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR -# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, -# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, -# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; -# OR BUSINESS INTERRUPTION). HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, -# WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR -# OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF -# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - - -__author__ = "KV Thanjavur Bhaaskar, Naveen Purushotham" -__copyright__ = "Copyright 2018, Xilinx" -__email__ = "kvt@xilinx.com, npurusho@xilinx.com" - -from .spyn import SpynOverlay \ No newline at end of file diff --git a/boards/Ultra96/spyn.bit b/boards/Ultra96/spyn.bit deleted file mode 100644 index 2cf3ca4..0000000 Binary files a/boards/Ultra96/spyn.bit and /dev/null differ diff --git a/boards/Ultra96/spyn.tcl b/boards/Ultra96/spyn.tcl deleted file mode 100644 index 68ef62e..0000000 --- a/boards/Ultra96/spyn.tcl +++ /dev/null @@ -1,2324 +0,0 @@ - -################################################################ -# This is a generated script based on design: zsys -# -# Though there are limitations about the generated script, -# the main purpose of this utility is to make learning -# IP Integrator Tcl commands easier. -################################################################ - -namespace eval _tcl { -proc get_script_folder {} { - set script_path [file normalize [info script]] - set script_folder [file dirname $script_path] - return $script_folder -} -} -variable script_folder -set script_folder [_tcl::get_script_folder] - -################################################################ -# Check if script is running in correct Vivado version. -################################################################ -set scripts_vivado_version 2018.2 -set current_vivado_version [version -short] - -if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { - puts "" - catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} - - return 1 -} - -################################################################ -# START -################################################################ - -# To test this script, run the following commands from Vivado Tcl console: -# source zsys_script.tcl - -# If there is no project opened, this script will create a -# project, but make sure you do not have an existing project -# <./myproj/project_1.xpr> in the current working folder. - -set list_projs [get_projects -quiet] -if { $list_projs eq "" } { - create_project project_1 myproj -part xczu3eg-sbva484-1-e - set_property BOARD_PART em.avnet.com:ultra96v1:part0:1.2 [current_project] -} - - -# CHANGE DESIGN NAME HERE -variable design_name -set design_name zsys - -# If you do not already have an existing IP Integrator design open, -# you can create a design using the following command: -# create_bd_design $design_name - -# Creating design if needed -set errMsg "" -set nRet 0 - -set cur_design [current_bd_design -quiet] -set list_cells [get_bd_cells -quiet] - -if { ${design_name} eq "" } { - # USE CASES: - # 1) Design_name not set - - set errMsg "Please set the variable to a non-empty value." - set nRet 1 - -} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { - # USE CASES: - # 2): Current design opened AND is empty AND names same. - # 3): Current design opened AND is empty AND names diff; design_name NOT in project. - # 4): Current design opened AND is empty AND names diff; design_name exists in project. - - if { $cur_design ne $design_name } { - common::send_msg_id "BD_TCL-001" "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." - set design_name [get_property NAME $cur_design] - } - common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." - -} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { - # USE CASES: - # 5) Current design opened AND has components AND same names. - - set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." - set nRet 1 -} elseif { [get_files -quiet ${design_name}.bd] ne "" } { - # USE CASES: - # 6) Current opened design, has components, but diff names, design_name exists in project. - # 7) No opened design, design_name exists in project. - - set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." - set nRet 2 - -} else { - # USE CASES: - # 8) No opened design, design_name not in project. - # 9) Current opened design, has components, but diff names, design_name not in project. - - common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." - - create_bd_design $design_name - - common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." - current_bd_design $design_name - -} - -common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable is equal to \"$design_name\"." - -if { $nRet != 0 } { - catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} - return $nRet -} - -set bCheckIPsPassed 1 -################################################################## -# CHECK IPs -################################################################## -set bCheckIPs 1 -if { $bCheckIPs == 1 } { - set list_check_ips "\ -trenz.biz:user:AXI_StreamCapture:1.0\ -trenz.biz:user:axis_concat:1.0\ -xilinx.com:ip:xlslice:1.0\ -xilinx.com:ip:xlconcat:2.1\ -xilinx.com:ip:axis_subset_converter:1.1\ -xilinx.com:ip:axi_datamover:5.1\ -trenz.biz:user:axi_reg32:1.0\ -trenz.biz:user:axis_AD7403:1.1\ -xilinx.com:ip:axis_broadcaster:1.1\ -xilinx.com:ip:axis_data_fifo:1.1\ -trenz.biz:user:axis_decimate:1.0\ -trenz.biz:user:axis_encoder:1.0\ -trenz.biz:user:axis_monitor:1.0\ -trenz.biz:user:axis_pwm:1.0\ -trenz.biz:user:clk_mux:1.0\ -xilinx.com:ip:clk_wiz:6.0\ -xilinx.com:ip:proc_sys_reset:5.0\ -xilinx.com:ip:zynq_ultra_ps_e:3.2\ -trenz.biz:user:rpm_check:1.0\ -xilinx.com:ip:vio:3.0\ -xilinx.com:ip:xlconstant:1.1\ -trenz.biz:hls:Clarke_Direct:1.0\ -trenz.biz:hls:Clarke_Inverse:1.0\ -trenz.biz:hls:Filters:1.0\ -trenz.biz:hls:PI_Control:1.0\ -trenz.biz:hls:Park_Direct:1.0\ -trenz.biz:hls:Park_Inverse:1.0\ -trenz.biz:hls:SVPWM:1.0\ -trenz.biz:user:foc_control:1.0\ -" - - set list_ips_missing "" - common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." - - foreach ip_vlnv $list_check_ips { - set ip_obj [get_ipdefs -all $ip_vlnv] - if { $ip_obj eq "" } { - lappend list_ips_missing $ip_vlnv - } - } - - if { $list_ips_missing ne "" } { - catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } - set bCheckIPsPassed 0 - } - -} - -if { $bCheckIPsPassed != 1 } { - common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above." - return 3 -} - -################################################################## -# DESIGN PROCs -################################################################## - - -# Hierarchical cell: FOC -proc create_hier_cell_FOC { parentCell nameHier } { - - variable script_folder - - if { $parentCell eq "" || $nameHier eq "" } { - catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_FOC() - Empty argument(s)!"} - return - } - - # Get object for parentCell - set parentObj [get_bd_cells $parentCell] - if { $parentObj == "" } { - catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} - return - } - - # Make sure parentObj is hier blk - set parentType [get_property TYPE $parentObj] - if { $parentType ne "hier" } { - catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} - return - } - - # Save current instance; Restore later - set oldCurInst [current_bd_instance .] - - # Set parent object as current - current_bd_instance $parentObj - - # Create cell and set as current instance - set hier_obj [create_bd_cell -type hier $nameHier] - current_bd_instance $hier_obj - - # Create interface pins - create_bd_intf_pin -mode Monitor -vlnv xilinx.com:interface:axis_rtl:1.0 SLOT_0_AXIS - create_bd_intf_pin -mode Monitor -vlnv xilinx.com:interface:axis_rtl:1.0 SLOT_0_AXIS1 - create_bd_intf_pin -mode Monitor -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis - create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 m_axis_V - create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_V - create_bd_intf_pin -mode Monitor -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_V1 - create_bd_intf_pin -mode Monitor -vlnv xilinx.com:interface:axis_rtl:1.0 s_axis_V2 - - # Create pins - create_bd_pin -dir I -from 31 -to 0 Flux_Ki - create_bd_pin -dir I -from 31 -to 0 Flux_Kp - create_bd_pin -dir I -from 31 -to 0 Flux_Sp - create_bd_pin -dir O -from 31 -to 0 -type data Id_out - create_bd_pin -dir O -from 31 -to 0 -type data Iq_out - create_bd_pin -dir O -from 31 -to 0 RPM - create_bd_pin -dir I -from 31 -to 0 RPM_Ki - create_bd_pin -dir I -from 31 -to 0 RPM_Kp - create_bd_pin -dir I -from 31 -to 0 RPM_Sp - create_bd_pin -dir I -from 31 -to 0 Torque_Ki - create_bd_pin -dir I -from 31 -to 0 Torque_Kp - create_bd_pin -dir I -from 31 -to 0 Torque_Sp - create_bd_pin -dir I -from 31 -to 0 Vd - create_bd_pin -dir I -from 31 -to 0 Vq - create_bd_pin -dir I -type clk ap_clk - create_bd_pin -dir I -type rst ap_rst_n - create_bd_pin -dir I -from 31 -to 0 -type data control - - # Create instance: Clarke_Direct_0, and set properties - set Clarke_Direct_0 [ create_bd_cell -type ip -vlnv trenz.biz:hls:Clarke_Direct:1.0 Clarke_Direct_0 ] - - # Create instance: Clarke_Inverse_0, and set properties - set Clarke_Inverse_0 [ create_bd_cell -type ip -vlnv trenz.biz:hls:Clarke_Inverse:1.0 Clarke_Inverse_0 ] - - # Create instance: Filters_0, and set properties - set Filters_0 [ create_bd_cell -type ip -vlnv trenz.biz:hls:Filters:1.0 Filters_0 ] - - # Create instance: Flux_Ki_slice, and set properties - set Flux_Ki_slice [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 Flux_Ki_slice ] - set_property -dict [ list \ - CONFIG.DIN_FROM {15} \ - CONFIG.DOUT_WIDTH {16} \ - ] $Flux_Ki_slice - - # Create instance: Flux_Kp_slice, and set properties - set Flux_Kp_slice [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 Flux_Kp_slice ] - set_property -dict [ list \ - CONFIG.DIN_FROM {15} \ - CONFIG.DOUT_WIDTH {16} \ - ] $Flux_Kp_slice - - # Create instance: Flux_PI_Control, and set properties - set Flux_PI_Control [ create_bd_cell -type ip -vlnv trenz.biz:hls:PI_Control:1.0 Flux_PI_Control ] - - # Create instance: Flux_Sp_slice, and set properties - set Flux_Sp_slice [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 Flux_Sp_slice ] - set_property -dict [ list \ - CONFIG.DIN_FROM {15} \ - CONFIG.DOUT_WIDTH {16} \ - ] $Flux_Sp_slice - - # Create instance: Park_Direct_0, and set properties - set Park_Direct_0 [ create_bd_cell -type ip -vlnv trenz.biz:hls:Park_Direct:1.0 Park_Direct_0 ] - - # Create instance: Park_Inverse_0, and set properties - set Park_Inverse_0 [ create_bd_cell -type ip -vlnv trenz.biz:hls:Park_Inverse:1.0 Park_Inverse_0 ] - - # Create instance: RPM_Ki_slice, and set properties - set RPM_Ki_slice [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 RPM_Ki_slice ] - set_property -dict [ list \ - CONFIG.DIN_FROM {15} \ - CONFIG.DOUT_WIDTH {16} \ - ] $RPM_Ki_slice - - # Create instance: RPM_Kp_slice, and set properties - set RPM_Kp_slice [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 RPM_Kp_slice ] - set_property -dict [ list \ - CONFIG.DIN_FROM {15} \ - CONFIG.DOUT_WIDTH {16} \ - ] $RPM_Kp_slice - - # Create instance: RPM_PI_Control, and set properties - set RPM_PI_Control [ create_bd_cell -type ip -vlnv trenz.biz:hls:PI_Control:1.0 RPM_PI_Control ] - - # Create instance: RPM_Sp_slice, and set properties - set RPM_Sp_slice [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 RPM_Sp_slice ] - set_property -dict [ list \ - CONFIG.DIN_FROM {15} \ - CONFIG.DOUT_WIDTH {16} \ - ] $RPM_Sp_slice - - # Create instance: SVPWM_0, and set properties - set SVPWM_0 [ create_bd_cell -type ip -vlnv trenz.biz:hls:SVPWM:1.0 SVPWM_0 ] - - # Create instance: Torque_Ki_slice, and set properties - set Torque_Ki_slice [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 Torque_Ki_slice ] - set_property -dict [ list \ - CONFIG.DIN_FROM {15} \ - CONFIG.DOUT_WIDTH {16} \ - ] $Torque_Ki_slice - - # Create instance: Torque_Kp_slice, and set properties - set Torque_Kp_slice [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 Torque_Kp_slice ] - set_property -dict [ list \ - CONFIG.DIN_FROM {15} \ - CONFIG.DOUT_WIDTH {16} \ - ] $Torque_Kp_slice - - # Create instance: Torque_PI_Control, and set properties - set Torque_PI_Control [ create_bd_cell -type ip -vlnv trenz.biz:hls:PI_Control:1.0 Torque_PI_Control ] - - # Create instance: Torque_Sp_slice, and set properties - set Torque_Sp_slice [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 Torque_Sp_slice ] - set_property -dict [ list \ - CONFIG.DIN_FROM {15} \ - CONFIG.DOUT_WIDTH {16} \ - ] $Torque_Sp_slice - - # Create instance: axis_broadcaster_0, and set properties - set axis_broadcaster_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_broadcaster:1.1 axis_broadcaster_0 ] - set_property -dict [ list \ - CONFIG.M00_TDATA_REMAP {tdata[15:0]} \ - CONFIG.M01_TDATA_REMAP {tdata[31:16]} \ - CONFIG.M02_TDATA_REMAP {tdata[47:32]} \ - CONFIG.M03_TDATA_REMAP {tdata[63:48]} \ - CONFIG.M_TDATA_NUM_BYTES {2} \ - CONFIG.NUM_MI {4} \ - CONFIG.S_TDATA_NUM_BYTES {8} \ - ] $axis_broadcaster_0 - - # Create instance: flux_limit, and set properties - set flux_limit [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 flux_limit ] - set_property -dict [ list \ - CONFIG.CONST_VAL {16777215} \ - CONFIG.CONST_WIDTH {32} \ - ] $flux_limit - - # Create instance: foc_control_0, and set properties - set foc_control_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:foc_control:1.0 foc_control_0 ] - - # Create instance: mode_concat_0, and set properties - set mode_concat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 mode_concat_0 ] - set_property -dict [ list \ - CONFIG.IN0_WIDTH {3} \ - CONFIG.IN1_WIDTH {29} \ - ] $mode_concat_0 - - # Create instance: mode_slice, and set properties - set mode_slice [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 mode_slice ] - set_property -dict [ list \ - CONFIG.DIN_FROM {2} \ - CONFIG.DOUT_WIDTH {3} \ - ] $mode_slice - - # Create instance: one, and set properties - set one [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 one ] - - # Create instance: rpm_limit, and set properties - set rpm_limit [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 rpm_limit ] - set_property -dict [ list \ - CONFIG.CONST_VAL {16777215} \ - CONFIG.CONST_WIDTH {32} \ - ] $rpm_limit - - # Create instance: torque_limit, and set properties - set torque_limit [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 torque_limit ] - set_property -dict [ list \ - CONFIG.CONST_VAL {16777215} \ - CONFIG.CONST_WIDTH {32} \ - ] $torque_limit - - # Create instance: xlconstant_0, and set properties - set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] - set_property -dict [ list \ - CONFIG.CONST_VAL {0} \ - CONFIG.CONST_WIDTH {29} \ - ] $xlconstant_0 - - # Create interface connections - connect_bd_intf_net -intf_net Clarke_Direct_0_m_axis_V [get_bd_intf_pins Clarke_Direct_0/m_axis_V] [get_bd_intf_pins Park_Direct_0/s_axis_V] - connect_bd_intf_net -intf_net [get_bd_intf_nets Clarke_Direct_0_m_axis_V] [get_bd_intf_pins s_axis_V1] [get_bd_intf_pins Clarke_Direct_0/m_axis_V] - connect_bd_intf_net -intf_net Clarke_Inverse_0_m_axis_V [get_bd_intf_pins Clarke_Inverse_0/m_axis_V] [get_bd_intf_pins SVPWM_0/s_axis_V] - connect_bd_intf_net -intf_net [get_bd_intf_nets Clarke_Inverse_0_m_axis_V] [get_bd_intf_pins SLOT_0_AXIS1] [get_bd_intf_pins Clarke_Inverse_0/m_axis_V] - connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins s_axis_V] [get_bd_intf_pins Filters_0/s_axis_V] - connect_bd_intf_net -intf_net Conn3 [get_bd_intf_pins m_axis_V] [get_bd_intf_pins SVPWM_0/m_axis_V] - connect_bd_intf_net -intf_net Filters_0_m_axis_V [get_bd_intf_pins Clarke_Direct_0/s_axis_V] [get_bd_intf_pins Filters_0/m_axis_V] - connect_bd_intf_net -intf_net Flux_PI_Control_m_axis_V [get_bd_intf_pins Flux_PI_Control/m_axis_V] [get_bd_intf_pins foc_control_0/s_flux] - connect_bd_intf_net -intf_net Park_Direct_0_m_axis_V [get_bd_intf_pins Park_Direct_0/m_axis_V] [get_bd_intf_pins axis_broadcaster_0/S_AXIS] - connect_bd_intf_net -intf_net [get_bd_intf_nets Park_Direct_0_m_axis_V] [get_bd_intf_pins SLOT_0_AXIS] [get_bd_intf_pins axis_broadcaster_0/S_AXIS] - connect_bd_intf_net -intf_net Park_Inverse_0_m_axis_V [get_bd_intf_pins Clarke_Inverse_0/s_axis_V] [get_bd_intf_pins Park_Inverse_0/m_axis_V] - connect_bd_intf_net -intf_net [get_bd_intf_nets Park_Inverse_0_m_axis_V] [get_bd_intf_pins s_axis_V2] [get_bd_intf_pins Park_Inverse_0/m_axis_V] - connect_bd_intf_net -intf_net RPM_PI_Control_m_axis_V [get_bd_intf_pins RPM_PI_Control/m_axis_V] [get_bd_intf_pins foc_control_0/s_rpm] - connect_bd_intf_net -intf_net Torque_PI_Control_m_axis_V [get_bd_intf_pins Torque_PI_Control/m_axis_V] [get_bd_intf_pins foc_control_0/s_torque] - connect_bd_intf_net -intf_net axis_broadcaster_0_M00_AXIS [get_bd_intf_pins Flux_PI_Control/s_axis_V] [get_bd_intf_pins axis_broadcaster_0/M00_AXIS] - connect_bd_intf_net -intf_net axis_broadcaster_0_M01_AXIS [get_bd_intf_pins Torque_PI_Control/s_axis_V] [get_bd_intf_pins axis_broadcaster_0/M01_AXIS] - connect_bd_intf_net -intf_net axis_broadcaster_0_M02_AXIS [get_bd_intf_pins RPM_PI_Control/s_axis_V] [get_bd_intf_pins axis_broadcaster_0/M02_AXIS] - connect_bd_intf_net -intf_net axis_broadcaster_0_M03_AXIS [get_bd_intf_pins axis_broadcaster_0/M03_AXIS] [get_bd_intf_pins foc_control_0/s_angle] - connect_bd_intf_net -intf_net foc_control_0_m_axis [get_bd_intf_pins Park_Inverse_0/s_axis_V] [get_bd_intf_pins foc_control_0/m_axis] - connect_bd_intf_net -intf_net [get_bd_intf_nets foc_control_0_m_axis] [get_bd_intf_pins m_axis] [get_bd_intf_pins foc_control_0/m_axis] - - # Create port connections - connect_bd_net -net Din1_1 [get_bd_pins RPM_Kp] [get_bd_pins RPM_Kp_slice/Din] - connect_bd_net -net Din2_1 [get_bd_pins RPM_Ki] [get_bd_pins RPM_Ki_slice/Din] - connect_bd_net -net Din3_1 [get_bd_pins Flux_Sp] [get_bd_pins Flux_Sp_slice/Din] - connect_bd_net -net Din4_1 [get_bd_pins Flux_Kp] [get_bd_pins Flux_Kp_slice/Din] - connect_bd_net -net Din5_1 [get_bd_pins Flux_Ki] [get_bd_pins Flux_Ki_slice/Din] - connect_bd_net -net Din6_1 [get_bd_pins Torque_Kp] [get_bd_pins Torque_Kp_slice/Din] - connect_bd_net -net Din7_1 [get_bd_pins Torque_Ki] [get_bd_pins Torque_Ki_slice/Din] - connect_bd_net -net Din_1 [get_bd_pins RPM_Sp] [get_bd_pins RPM_Sp_slice/Din] - connect_bd_net -net Filters_0_RPM_out [get_bd_pins RPM] [get_bd_pins Filters_0/RPM_out] - connect_bd_net -net Flux_Ki_slice_Dout [get_bd_pins Flux_Ki_slice/Dout] [get_bd_pins Flux_PI_Control/Ki] - connect_bd_net -net Flux_Kp_slice_Dout [get_bd_pins Flux_Kp_slice/Dout] [get_bd_pins Flux_PI_Control/Kp] - connect_bd_net -net Flux_Sp_slice_Dout [get_bd_pins Flux_PI_Control/Sp] [get_bd_pins Flux_Sp_slice/Dout] - connect_bd_net -net Park_Direct_0_Id_out [get_bd_pins Id_out] [get_bd_pins Park_Direct_0/Id_out] - connect_bd_net -net Park_Direct_0_Iq_out [get_bd_pins Iq_out] [get_bd_pins Park_Direct_0/Iq_out] - connect_bd_net -net RPM_Ki_slice_Dout [get_bd_pins RPM_Ki_slice/Dout] [get_bd_pins RPM_PI_Control/Ki] - connect_bd_net -net RPM_Kp_slice_Dout [get_bd_pins RPM_Kp_slice/Dout] [get_bd_pins RPM_PI_Control/Kp] - connect_bd_net -net RPM_Sp_slice_Dout [get_bd_pins RPM_PI_Control/Sp] [get_bd_pins RPM_Sp_slice/Dout] - connect_bd_net -net Torque_Ki_slice_Dout [get_bd_pins Torque_Ki_slice/Dout] [get_bd_pins Torque_PI_Control/Ki] - connect_bd_net -net Torque_Kp_slice_Dout [get_bd_pins Torque_Kp_slice/Dout] [get_bd_pins Torque_PI_Control/Kp] - connect_bd_net -net Torque_Sp_1 [get_bd_pins Torque_Sp] [get_bd_pins Torque_Sp_slice/Din] - connect_bd_net -net Torque_Sp_slice_Dout [get_bd_pins Torque_Sp_slice/Dout] [get_bd_pins foc_control_0/torque_sp_in] - connect_bd_net -net Vd_1 [get_bd_pins Vd] [get_bd_pins foc_control_0/vd_in] - connect_bd_net -net Vq_1 [get_bd_pins Vq] [get_bd_pins foc_control_0/vq_in] - connect_bd_net -net ap_clk_1 [get_bd_pins ap_clk] [get_bd_pins Clarke_Direct_0/ap_clk] [get_bd_pins Clarke_Inverse_0/ap_clk] [get_bd_pins Filters_0/ap_clk] [get_bd_pins Flux_PI_Control/ap_clk] [get_bd_pins Park_Direct_0/ap_clk] [get_bd_pins Park_Inverse_0/ap_clk] [get_bd_pins RPM_PI_Control/ap_clk] [get_bd_pins SVPWM_0/ap_clk] [get_bd_pins Torque_PI_Control/ap_clk] [get_bd_pins axis_broadcaster_0/aclk] [get_bd_pins foc_control_0/axis_aclk] - connect_bd_net -net ap_rst_n_1 [get_bd_pins ap_rst_n] [get_bd_pins Clarke_Direct_0/ap_rst_n] [get_bd_pins Clarke_Inverse_0/ap_rst_n] [get_bd_pins Filters_0/ap_rst_n] [get_bd_pins Flux_PI_Control/ap_rst_n] [get_bd_pins Park_Direct_0/ap_rst_n] [get_bd_pins Park_Inverse_0/ap_rst_n] [get_bd_pins RPM_PI_Control/ap_rst_n] [get_bd_pins SVPWM_0/ap_rst_n] [get_bd_pins Torque_PI_Control/ap_rst_n] [get_bd_pins axis_broadcaster_0/aresetn] [get_bd_pins foc_control_0/axis_aresetn] - connect_bd_net -net control_1 [get_bd_pins control] [get_bd_pins foc_control_0/control_in] [get_bd_pins mode_slice/Din] - connect_bd_net -net flux_limit_dout [get_bd_pins Flux_PI_Control/limit] [get_bd_pins flux_limit/dout] - connect_bd_net -net foc_control_0_torque_sp_out [get_bd_pins Torque_PI_Control/Sp] [get_bd_pins foc_control_0/torque_sp_out] - connect_bd_net -net mode_concat_0_dout [get_bd_pins Filters_0/control] [get_bd_pins Flux_PI_Control/mode] [get_bd_pins RPM_PI_Control/mode] [get_bd_pins Torque_PI_Control/mode] [get_bd_pins mode_concat_0/dout] - connect_bd_net -net one_dout [get_bd_pins Clarke_Direct_0/ap_start] [get_bd_pins Clarke_Inverse_0/ap_start] [get_bd_pins Filters_0/ap_start] [get_bd_pins Flux_PI_Control/ap_start] [get_bd_pins Park_Direct_0/ap_start] [get_bd_pins Park_Inverse_0/ap_start] [get_bd_pins RPM_PI_Control/ap_start] [get_bd_pins SVPWM_0/ap_start] [get_bd_pins Torque_PI_Control/ap_start] [get_bd_pins one/dout] - connect_bd_net -net rpm_limit_dout [get_bd_pins RPM_PI_Control/limit] [get_bd_pins rpm_limit/dout] - connect_bd_net -net torque_limit_dout [get_bd_pins Torque_PI_Control/limit] [get_bd_pins torque_limit/dout] - connect_bd_net -net xlconstant_0_dout [get_bd_pins mode_concat_0/In1] [get_bd_pins xlconstant_0/dout] - connect_bd_net -net xlslice_0_Dout [get_bd_pins mode_concat_0/In0] [get_bd_pins mode_slice/Dout] - - # Restore current instance - current_bd_instance $oldCurInst -} - - -# Procedure to create entire design; Provide argument to make -# procedure reusable. If parentCell is "", will use root. -proc create_root_design { parentCell } { - - variable script_folder - variable design_name - - if { $parentCell eq "" } { - set parentCell [get_bd_cells /] - } - - # Get object for parentCell - set parentObj [get_bd_cells $parentCell] - if { $parentObj == "" } { - catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} - return - } - - # Make sure parentObj is hier blk - set parentType [get_property TYPE $parentObj] - if { $parentType ne "hier" } { - catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} - return - } - - # Save current instance; Restore later - set oldCurInst [current_bd_instance .] - - # Set parent object as current - current_bd_instance $parentObj - - - # Create interface ports - - # Create ports - set BT_ctsn [ create_bd_port -dir I BT_ctsn ] - set BT_rtsn [ create_bd_port -dir O BT_rtsn ] - set ENC_A [ create_bd_port -dir I ENC_A ] - set ENC_B [ create_bd_port -dir I ENC_B ] - set ENC_I [ create_bd_port -dir I ENC_I ] - set GH [ create_bd_port -dir O -from 2 -to 0 GH ] - set GL [ create_bd_port -dir O -from 2 -to 0 GL ] - set SCLK [ create_bd_port -dir O SCLK ] - set SDI1 [ create_bd_port -dir I SDI1 ] - set SDI2 [ create_bd_port -dir I SDI2 ] - set SDI3 [ create_bd_port -dir I SDI3 ] - set SDV [ create_bd_port -dir I SDV ] - - # Create instance: AXI_StreamCapture_0, and set properties - set AXI_StreamCapture_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:AXI_StreamCapture:1.0 AXI_StreamCapture_0 ] - - # Create instance: Angle_RPM_Ib_Ia, and set properties - set Angle_RPM_Ib_Ia [ create_bd_cell -type ip -vlnv trenz.biz:user:axis_concat:1.0 Angle_RPM_Ib_Ia ] - set_property -dict [ list \ - CONFIG.C_A_TDATA_WIDTH {32} \ - CONFIG.C_IN_CHANNELS {3} \ - CONFIG.M_TDATA_WIDTH {64} \ - ] $Angle_RPM_Ib_Ia - - # Create instance: Angle_Shift_slice, and set properties - set Angle_Shift_slice [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 Angle_Shift_slice ] - set_property -dict [ list \ - CONFIG.DIN_FROM {15} \ - CONFIG.DOUT_WIDTH {16} \ - ] $Angle_Shift_slice - - # Create instance: Angle_concat, and set properties - set Angle_concat [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 Angle_concat ] - set_property -dict [ list \ - CONFIG.IN0_WIDTH {16} \ - CONFIG.IN1_WIDTH {16} \ - ] $Angle_concat - - # Create instance: FOC - create_hier_cell_FOC [current_bd_instance .] FOC - - # Create instance: Ib_Ia, and set properties - set Ib_Ia [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_subset_converter:1.1 Ib_Ia ] - set_property -dict [ list \ - CONFIG.M_TDATA_NUM_BYTES {4} \ - CONFIG.S_TDATA_NUM_BYTES {8} \ - CONFIG.TDATA_REMAP {tdata[31:0]} \ - ] $Ib_Ia - - # Create instance: axi_datamover_0, and set properties - set axi_datamover_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_datamover:5.1 axi_datamover_0 ] - set_property -dict [ list \ - CONFIG.c_dummy {0} \ - CONFIG.c_enable_mm2s {0} \ - CONFIG.c_include_mm2s {Omit} \ - CONFIG.c_include_mm2s_stsfifo {false} \ - CONFIG.c_m_axi_s2mm_id_width {0} \ - CONFIG.c_mm2s_include_sf {false} \ - CONFIG.c_s2mm_btt_used {23} \ - CONFIG.c_s2mm_burst_size {8} \ - CONFIG.c_s2mm_support_indet_btt {true} \ - ] $axi_datamover_0 - - # Create instance: axi_interconnect_0, and set properties - set axi_interconnect_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_0 ] - set_property -dict [ list \ - CONFIG.NUM_MI {1} \ - CONFIG.SYNCHRONIZATION_STAGES {2} \ - ] $axi_interconnect_0 - - # Create instance: axi_reg32_0, and set properties - set axi_reg32_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:axi_reg32:1.0 axi_reg32_0 ] - set_property -dict [ list \ - CONFIG.C_NUM_RO_REG {5} \ - CONFIG.C_NUM_WR_REG {16} \ - CONFIG.C_WR0_ALIAS {Control} \ - CONFIG.C_WR10_ALIAS {Angle Shift} \ - CONFIG.C_WR10_DEFAULT {719} \ - CONFIG.C_WR11_ALIAS {Vd} \ - CONFIG.C_WR11_DEFAULT {-7424} \ - CONFIG.C_WR12_ALIAS {Vq} \ - CONFIG.C_WR12_DEFAULT {15000} \ - CONFIG.C_WR13_ALIAS {Decimation} \ - CONFIG.C_WR14_ALIAS {TR_Control} \ - CONFIG.C_WR1_ALIAS {Flux Sp} \ - CONFIG.C_WR2_ALIAS {Flux Kp} \ - CONFIG.C_WR2_DEFAULT {-45056} \ - CONFIG.C_WR3_ALIAS {Flux Ki} \ - CONFIG.C_WR4_ALIAS {Torque Sp} \ - CONFIG.C_WR4_DEFAULT {100} \ - CONFIG.C_WR5_ALIAS {Torque Kp} \ - CONFIG.C_WR5_DEFAULT {256} \ - CONFIG.C_WR6_ALIAS {Torque Ki} \ - CONFIG.C_WR7_ALIAS {RPM Sp} \ - CONFIG.C_WR7_DEFAULT {3000} \ - CONFIG.C_WR8_ALIAS {RPM Kp} \ - CONFIG.C_WR8_DEFAULT {744} \ - CONFIG.C_WR9_ALIAS {RPM Ki} \ - CONFIG.C_WR9_DEFAULT {9} \ - ] $axi_reg32_0 - - # Create instance: axis_AD7403_0, and set properties - set axis_AD7403_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:axis_AD7403:1.1 axis_AD7403_0 ] - set_property -dict [ list \ - CONFIG.C_CLOCK_RATIO {5} \ - CONFIG.C_DECIMATION {128} \ - CONFIG.C_SIGNED {true} \ - ] $axis_AD7403_0 - - # Create instance: axis_broadcaster_0, and set properties - set axis_broadcaster_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_broadcaster:1.1 axis_broadcaster_0 ] - set_property -dict [ list \ - CONFIG.M00_TDATA_REMAP {tdata[63:0]} \ - CONFIG.M01_TDATA_REMAP {tdata[63:0]} \ - CONFIG.M_TDATA_NUM_BYTES {8} \ - CONFIG.S_TDATA_NUM_BYTES {8} \ - ] $axis_broadcaster_0 - - # Create instance: axis_data_fifo_0, and set properties - set axis_data_fifo_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:1.1 axis_data_fifo_0 ] - set_property -dict [ list \ - CONFIG.FIFO_DEPTH {4096} \ - ] $axis_data_fifo_0 - - # Create instance: axis_data_fifo_1, and set properties - set axis_data_fifo_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:1.1 axis_data_fifo_1 ] - set_property -dict [ list \ - CONFIG.IS_ACLK_ASYNC {1} \ - ] $axis_data_fifo_1 - - # Create instance: axis_decimate_0, and set properties - set axis_decimate_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:axis_decimate:1.0 axis_decimate_0 ] - set_property -dict [ list \ - CONFIG.C_TDATA_WIDTH {64} \ - ] $axis_decimate_0 - - # Create instance: axis_encoder_0, and set properties - set axis_encoder_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:axis_encoder:1.0 axis_encoder_0 ] - set_property -dict [ list \ - CONFIG.C_ANGLE_AXIS {true} \ - CONFIG.C_CPR {1000} \ - CONFIG.C_RPM_AXIS {true} \ - CONFIG.C_USE_SHIFT {true} \ - ] $axis_encoder_0 - - # Create instance: axis_monitor_0, and set properties - set axis_monitor_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:axis_monitor:1.0 axis_monitor_0 ] - set_property -dict [ list \ - CONFIG.C_SLAVE_IF {7} \ - ] $axis_monitor_0 - - # Create instance: axis_pwm_0, and set properties - set axis_pwm_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:axis_pwm:1.0 axis_pwm_0 ] - set_property -dict [ list \ - CONFIG.C_CHANNELS {3} \ - CONFIG.C_DEADTIME_SYCLES {50} \ - CONFIG.C_IN_TYPE {1} \ - CONFIG.C_S_AXIS_TDATA_WIDTH {64} \ - ] $axis_pwm_0 - - # Create instance: clk_mux_0, and set properties - set clk_mux_0 [ create_bd_cell -type ip -vlnv trenz.biz:user:clk_mux:1.0 clk_mux_0 ] - - # Create instance: clk_wiz_0, and set properties - set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0 ] - set_property -dict [ list \ - CONFIG.CLKOUT1_DRIVES {BUFG} \ - CONFIG.CLKOUT1_JITTER {149.658} \ - CONFIG.CLKOUT1_PHASE_ERROR {403.700} \ - CONFIG.CLKOUT1_REQUESTED_DUTY_CYCLE {50.0} \ - CONFIG.CLKOUT2_DRIVES {Buffer} \ - CONFIG.CLKOUT3_DRIVES {Buffer} \ - CONFIG.CLKOUT4_DRIVES {Buffer} \ - CONFIG.CLKOUT5_DRIVES {Buffer} \ - CONFIG.CLKOUT6_DRIVES {Buffer} \ - CONFIG.CLKOUT7_DRIVES {Buffer} \ - CONFIG.MMCM_BANDWIDTH {LOW} \ - CONFIG.MMCM_CLKFBOUT_MULT_F {21.000} \ - CONFIG.MMCM_CLKOUT0_DIVIDE_F {10.500} \ - CONFIG.MMCM_COMPENSATION {AUTO} \ - CONFIG.MMCM_DIVCLK_DIVIDE {2} \ - CONFIG.PHASESHIFT_MODE {WAVEFORM} \ - CONFIG.USE_LOCKED {false} \ - CONFIG.USE_PHASE_ALIGNMENT {true} \ - CONFIG.USE_RESET {false} \ - CONFIG.USE_SPREAD_SPECTRUM {true} \ - ] $clk_wiz_0 - - # Create instance: proc_sys_reset_0, and set properties - set proc_sys_reset_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_0 ] - - # Create instance: proc_sys_reset_1, and set properties - set proc_sys_reset_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 proc_sys_reset_1 ] - - # Create instance: ps7_0_axi_periph, and set properties - set ps7_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 ps7_0_axi_periph ] - set_property -dict [ list \ - CONFIG.NUM_MI {2} \ - CONFIG.SYNCHRONIZATION_STAGES {2} \ - ] $ps7_0_axi_periph - - # Create instance: psu, and set properties - set psu [ create_bd_cell -type ip -vlnv xilinx.com:ip:zynq_ultra_ps_e:3.2 psu ] - set_property -dict [ list \ - CONFIG.CAN0_BOARD_INTERFACE {custom} \ - CONFIG.CAN1_BOARD_INTERFACE {custom} \ - CONFIG.CSU_BOARD_INTERFACE {custom} \ - CONFIG.DP_BOARD_INTERFACE {custom} \ - CONFIG.GEM0_BOARD_INTERFACE {custom} \ - CONFIG.GEM1_BOARD_INTERFACE {custom} \ - CONFIG.GEM2_BOARD_INTERFACE {custom} \ - CONFIG.GEM3_BOARD_INTERFACE {custom} \ - CONFIG.GPIO_BOARD_INTERFACE {custom} \ - CONFIG.IIC0_BOARD_INTERFACE {custom} \ - CONFIG.IIC1_BOARD_INTERFACE {custom} \ - CONFIG.NAND_BOARD_INTERFACE {custom} \ - CONFIG.PCIE_BOARD_INTERFACE {custom} \ - CONFIG.PJTAG_BOARD_INTERFACE {custom} \ - CONFIG.PMU_BOARD_INTERFACE {custom} \ - CONFIG.PSU_BANK_0_IO_STANDARD {LVCMOS18} \ - CONFIG.PSU_BANK_1_IO_STANDARD {LVCMOS18} \ - CONFIG.PSU_BANK_2_IO_STANDARD {LVCMOS18} \ - CONFIG.PSU_BANK_3_IO_STANDARD {LVCMOS18} \ - CONFIG.PSU_DDR_RAM_HIGHADDR {0x7FFFFFFF} \ - CONFIG.PSU_DDR_RAM_HIGHADDR_OFFSET {0x00000002} \ - CONFIG.PSU_DDR_RAM_LOWADDR_OFFSET {0x80000000} \ - CONFIG.PSU_IMPORT_BOARD_PRESET {} \ - CONFIG.PSU_MIO_0_DIRECTION {out} \ - CONFIG.PSU_MIO_0_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_0_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_0_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_0_SLEW {slow} \ - CONFIG.PSU_MIO_10_DIRECTION {inout} \ - CONFIG.PSU_MIO_10_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_10_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_10_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_10_SLEW {slow} \ - CONFIG.PSU_MIO_11_DIRECTION {inout} \ - CONFIG.PSU_MIO_11_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_11_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_11_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_11_SLEW {slow} \ - CONFIG.PSU_MIO_12_DIRECTION {inout} \ - CONFIG.PSU_MIO_12_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_12_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_12_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_12_SLEW {slow} \ - CONFIG.PSU_MIO_13_DIRECTION {inout} \ - CONFIG.PSU_MIO_13_DRIVE_STRENGTH {4} \ - CONFIG.PSU_MIO_13_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_13_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_13_SLEW {slow} \ - CONFIG.PSU_MIO_14_DIRECTION {inout} \ - CONFIG.PSU_MIO_14_DRIVE_STRENGTH {4} \ - CONFIG.PSU_MIO_14_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_14_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_14_SLEW {slow} \ - CONFIG.PSU_MIO_15_DIRECTION {inout} \ - CONFIG.PSU_MIO_15_DRIVE_STRENGTH {4} \ - CONFIG.PSU_MIO_15_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_15_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_15_SLEW {slow} \ - CONFIG.PSU_MIO_16_DIRECTION {inout} \ - CONFIG.PSU_MIO_16_DRIVE_STRENGTH {4} \ - CONFIG.PSU_MIO_16_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_16_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_16_SLEW {slow} \ - CONFIG.PSU_MIO_17_DIRECTION {inout} \ - CONFIG.PSU_MIO_17_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_17_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_17_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_17_SLEW {slow} \ - CONFIG.PSU_MIO_18_DIRECTION {inout} \ - CONFIG.PSU_MIO_18_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_18_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_18_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_18_SLEW {slow} \ - CONFIG.PSU_MIO_19_DIRECTION {inout} \ - CONFIG.PSU_MIO_19_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_19_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_19_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_19_SLEW {slow} \ - CONFIG.PSU_MIO_1_DIRECTION {in} \ - CONFIG.PSU_MIO_1_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_1_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_1_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_1_SLEW {slow} \ - CONFIG.PSU_MIO_20_DIRECTION {inout} \ - CONFIG.PSU_MIO_20_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_20_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_20_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_20_SLEW {slow} \ - CONFIG.PSU_MIO_21_DIRECTION {inout} \ - CONFIG.PSU_MIO_21_DRIVE_STRENGTH {4} \ - CONFIG.PSU_MIO_21_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_21_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_21_SLEW {slow} \ - CONFIG.PSU_MIO_22_DIRECTION {out} \ - CONFIG.PSU_MIO_22_DRIVE_STRENGTH {4} \ - CONFIG.PSU_MIO_22_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_22_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_22_SLEW {slow} \ - CONFIG.PSU_MIO_23_DIRECTION {inout} \ - CONFIG.PSU_MIO_23_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_23_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_23_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_23_SLEW {slow} \ - CONFIG.PSU_MIO_24_DIRECTION {in} \ - CONFIG.PSU_MIO_24_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_24_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_24_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_24_SLEW {slow} \ - CONFIG.PSU_MIO_25_DIRECTION {inout} \ - CONFIG.PSU_MIO_25_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_25_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_25_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_25_SLEW {slow} \ - CONFIG.PSU_MIO_26_DIRECTION {in} \ - CONFIG.PSU_MIO_26_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_26_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_26_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_26_SLEW {slow} \ - CONFIG.PSU_MIO_27_DIRECTION {out} \ - CONFIG.PSU_MIO_27_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_27_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_27_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_27_SLEW {slow} \ - CONFIG.PSU_MIO_28_DIRECTION {in} \ - CONFIG.PSU_MIO_28_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_28_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_28_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_28_SLEW {slow} \ - CONFIG.PSU_MIO_29_DIRECTION {out} \ - CONFIG.PSU_MIO_29_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_29_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_29_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_29_SLEW {slow} \ - CONFIG.PSU_MIO_2_DIRECTION {in} \ - CONFIG.PSU_MIO_2_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_2_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_2_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_2_SLEW {slow} \ - CONFIG.PSU_MIO_30_DIRECTION {in} \ - CONFIG.PSU_MIO_30_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_30_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_30_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_30_SLEW {slow} \ - CONFIG.PSU_MIO_31_DIRECTION {inout} \ - CONFIG.PSU_MIO_31_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_31_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_31_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_31_SLEW {slow} \ - CONFIG.PSU_MIO_32_DIRECTION {out} \ - CONFIG.PSU_MIO_32_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_32_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_32_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_32_SLEW {slow} \ - CONFIG.PSU_MIO_33_DIRECTION {out} \ - CONFIG.PSU_MIO_33_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_33_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_33_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_33_SLEW {slow} \ - CONFIG.PSU_MIO_34_DIRECTION {out} \ - CONFIG.PSU_MIO_34_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_34_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_34_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_34_SLEW {slow} \ - CONFIG.PSU_MIO_35_DIRECTION {inout} \ - CONFIG.PSU_MIO_35_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_35_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_35_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_35_SLEW {slow} \ - CONFIG.PSU_MIO_36_DIRECTION {inout} \ - CONFIG.PSU_MIO_36_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_36_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_36_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_36_SLEW {slow} \ - CONFIG.PSU_MIO_37_DIRECTION {inout} \ - CONFIG.PSU_MIO_37_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_37_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_37_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_37_SLEW {slow} \ - CONFIG.PSU_MIO_38_DIRECTION {inout} \ - CONFIG.PSU_MIO_38_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_38_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_38_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_38_SLEW {slow} \ - CONFIG.PSU_MIO_39_DIRECTION {inout} \ - CONFIG.PSU_MIO_39_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_39_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_39_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_39_SLEW {slow} \ - CONFIG.PSU_MIO_3_DIRECTION {out} \ - CONFIG.PSU_MIO_3_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_3_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_3_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_3_SLEW {slow} \ - CONFIG.PSU_MIO_40_DIRECTION {inout} \ - CONFIG.PSU_MIO_40_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_40_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_40_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_40_SLEW {slow} \ - CONFIG.PSU_MIO_41_DIRECTION {inout} \ - CONFIG.PSU_MIO_41_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_41_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_41_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_41_SLEW {slow} \ - CONFIG.PSU_MIO_42_DIRECTION {inout} \ - CONFIG.PSU_MIO_42_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_42_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_42_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_42_SLEW {slow} \ - CONFIG.PSU_MIO_43_DIRECTION {inout} \ - CONFIG.PSU_MIO_43_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_43_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_43_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_43_SLEW {slow} \ - CONFIG.PSU_MIO_44_DIRECTION {inout} \ - CONFIG.PSU_MIO_44_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_44_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_44_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_44_SLEW {slow} \ - CONFIG.PSU_MIO_45_DIRECTION {inout} \ - CONFIG.PSU_MIO_45_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_45_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_45_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_45_SLEW {slow} \ - CONFIG.PSU_MIO_46_DIRECTION {inout} \ - CONFIG.PSU_MIO_46_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_46_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_46_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_46_SLEW {slow} \ - CONFIG.PSU_MIO_47_DIRECTION {inout} \ - CONFIG.PSU_MIO_47_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_47_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_47_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_47_SLEW {slow} \ - CONFIG.PSU_MIO_48_DIRECTION {inout} \ - CONFIG.PSU_MIO_48_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_48_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_48_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_48_SLEW {slow} \ - CONFIG.PSU_MIO_49_DIRECTION {inout} \ - CONFIG.PSU_MIO_49_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_49_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_49_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_49_SLEW {slow} \ - CONFIG.PSU_MIO_4_DIRECTION {inout} \ - CONFIG.PSU_MIO_4_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_4_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_4_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_4_SLEW {slow} \ - CONFIG.PSU_MIO_50_DIRECTION {inout} \ - CONFIG.PSU_MIO_50_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_50_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_50_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_50_SLEW {slow} \ - CONFIG.PSU_MIO_51_DIRECTION {out} \ - CONFIG.PSU_MIO_51_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_51_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_51_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_51_SLEW {slow} \ - CONFIG.PSU_MIO_52_DIRECTION {in} \ - CONFIG.PSU_MIO_52_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_52_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_52_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_52_SLEW {slow} \ - CONFIG.PSU_MIO_53_DIRECTION {in} \ - CONFIG.PSU_MIO_53_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_53_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_53_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_53_SLEW {slow} \ - CONFIG.PSU_MIO_54_DIRECTION {inout} \ - CONFIG.PSU_MIO_54_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_54_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_54_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_54_SLEW {slow} \ - CONFIG.PSU_MIO_55_DIRECTION {in} \ - CONFIG.PSU_MIO_55_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_55_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_55_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_55_SLEW {slow} \ - CONFIG.PSU_MIO_56_DIRECTION {inout} \ - CONFIG.PSU_MIO_56_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_56_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_56_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_56_SLEW {slow} \ - CONFIG.PSU_MIO_57_DIRECTION {inout} \ - CONFIG.PSU_MIO_57_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_57_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_57_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_57_SLEW {slow} \ - CONFIG.PSU_MIO_58_DIRECTION {out} \ - CONFIG.PSU_MIO_58_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_58_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_58_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_58_SLEW {slow} \ - CONFIG.PSU_MIO_59_DIRECTION {inout} \ - CONFIG.PSU_MIO_59_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_59_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_59_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_59_SLEW {slow} \ - CONFIG.PSU_MIO_5_DIRECTION {inout} \ - CONFIG.PSU_MIO_5_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_5_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_5_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_5_SLEW {slow} \ - CONFIG.PSU_MIO_60_DIRECTION {inout} \ - CONFIG.PSU_MIO_60_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_60_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_60_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_60_SLEW {slow} \ - CONFIG.PSU_MIO_61_DIRECTION {inout} \ - CONFIG.PSU_MIO_61_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_61_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_61_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_61_SLEW {slow} \ - CONFIG.PSU_MIO_62_DIRECTION {inout} \ - CONFIG.PSU_MIO_62_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_62_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_62_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_62_SLEW {slow} \ - CONFIG.PSU_MIO_63_DIRECTION {inout} \ - CONFIG.PSU_MIO_63_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_63_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_63_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_63_SLEW {slow} \ - CONFIG.PSU_MIO_64_DIRECTION {in} \ - CONFIG.PSU_MIO_64_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_64_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_64_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_64_SLEW {slow} \ - CONFIG.PSU_MIO_65_DIRECTION {in} \ - CONFIG.PSU_MIO_65_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_65_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_65_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_65_SLEW {slow} \ - CONFIG.PSU_MIO_66_DIRECTION {inout} \ - CONFIG.PSU_MIO_66_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_66_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_66_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_66_SLEW {slow} \ - CONFIG.PSU_MIO_67_DIRECTION {in} \ - CONFIG.PSU_MIO_67_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_67_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_67_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_67_SLEW {slow} \ - CONFIG.PSU_MIO_68_DIRECTION {inout} \ - CONFIG.PSU_MIO_68_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_68_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_68_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_68_SLEW {slow} \ - CONFIG.PSU_MIO_69_DIRECTION {inout} \ - CONFIG.PSU_MIO_69_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_69_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_69_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_69_SLEW {slow} \ - CONFIG.PSU_MIO_6_DIRECTION {inout} \ - CONFIG.PSU_MIO_6_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_6_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_6_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_6_SLEW {slow} \ - CONFIG.PSU_MIO_70_DIRECTION {out} \ - CONFIG.PSU_MIO_70_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_70_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_70_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_70_SLEW {slow} \ - CONFIG.PSU_MIO_71_DIRECTION {inout} \ - CONFIG.PSU_MIO_71_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_71_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_71_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_71_SLEW {slow} \ - CONFIG.PSU_MIO_72_DIRECTION {inout} \ - CONFIG.PSU_MIO_72_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_72_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_72_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_72_SLEW {slow} \ - CONFIG.PSU_MIO_73_DIRECTION {inout} \ - CONFIG.PSU_MIO_73_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_73_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_73_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_73_SLEW {slow} \ - CONFIG.PSU_MIO_74_DIRECTION {inout} \ - CONFIG.PSU_MIO_74_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_74_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_74_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_74_SLEW {slow} \ - CONFIG.PSU_MIO_75_DIRECTION {inout} \ - CONFIG.PSU_MIO_75_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_75_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_75_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_75_SLEW {slow} \ - CONFIG.PSU_MIO_76_DIRECTION {inout} \ - CONFIG.PSU_MIO_76_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_76_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_76_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_76_SLEW {slow} \ - CONFIG.PSU_MIO_77_DIRECTION {inout} \ - CONFIG.PSU_MIO_77_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_77_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_77_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_77_SLEW {slow} \ - CONFIG.PSU_MIO_7_DIRECTION {inout} \ - CONFIG.PSU_MIO_7_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_7_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_7_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_7_SLEW {slow} \ - CONFIG.PSU_MIO_8_DIRECTION {inout} \ - CONFIG.PSU_MIO_8_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_8_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_8_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_8_SLEW {slow} \ - CONFIG.PSU_MIO_9_DIRECTION {inout} \ - CONFIG.PSU_MIO_9_DRIVE_STRENGTH {12} \ - CONFIG.PSU_MIO_9_INPUT_TYPE {schmitt} \ - CONFIG.PSU_MIO_9_PULLUPDOWN {pullup} \ - CONFIG.PSU_MIO_9_SLEW {slow} \ - CONFIG.PSU_MIO_TREE_PERIPHERALS {UART 1#UART 1#UART 0#UART 0#I2C 1#I2C 1#SPI 1#GPIO0 MIO#GPIO0 MIO#SPI 1#SPI 1#SPI 1#GPIO0 MIO#SD 0#SD 0#SD 0#SD 0#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#GPIO0 MIO#SD 0#SD 0#GPIO0 MIO#SD 0#GPIO0 MIO#PMU GPI 0#DPAUX#DPAUX#DPAUX#DPAUX#GPIO1 MIO#PMU GPO 0#PMU GPO 1#PMU GPO 2#GPIO1 MIO#GPIO1 MIO#GPIO1 MIO#SPI 0#GPIO1 MIO#GPIO1 MIO#SPI 0#SPI 0#SPI 0#GPIO1 MIO#GPIO1 MIO#SD 1#SD 1#SD 1#SD 1#SD 1#SD 1#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 0#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#USB 1#GPIO2 MIO#GPIO2 MIO} \ - CONFIG.PSU_MIO_TREE_SIGNALS {txd#rxd#rxd#txd#scl_out#sda_out#sclk_out#gpio0[7]#gpio0[8]#n_ss_out[0]#miso#mosi#gpio0[12]#sdio0_data_out[0]#sdio0_data_out[1]#sdio0_data_out[2]#sdio0_data_out[3]#gpio0[17]#gpio0[18]#gpio0[19]#gpio0[20]#sdio0_cmd_out#sdio0_clk_out#gpio0[23]#sdio0_cd_n#gpio0[25]#gpi[0]#dp_aux_data_out#dp_hot_plug_detect#dp_aux_data_oe#dp_aux_data_in#gpio1[31]#gpo[0]#gpo[1]#gpo[2]#gpio1[35]#gpio1[36]#gpio1[37]#sclk_out#gpio1[39]#gpio1[40]#n_ss_out[0]#miso#mosi#gpio1[44]#gpio1[45]#sdio1_data_out[0]#sdio1_data_out[1]#sdio1_data_out[2]#sdio1_data_out[3]#sdio1_cmd_out#sdio1_clk_out#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#ulpi_clk_in#ulpi_dir#ulpi_tx_data[2]#ulpi_nxt#ulpi_tx_data[0]#ulpi_tx_data[1]#ulpi_stp#ulpi_tx_data[3]#ulpi_tx_data[4]#ulpi_tx_data[5]#ulpi_tx_data[6]#ulpi_tx_data[7]#gpio2[76]#gpio2[77]} \ - CONFIG.PSU_PERIPHERAL_BOARD_PRESET {} \ - CONFIG.PSU_SD0_INTERNAL_BUS_WIDTH {4} \ - CONFIG.PSU_SD1_INTERNAL_BUS_WIDTH {4} \ - CONFIG.PSU_SMC_CYCLE_T0 {NA} \ - CONFIG.PSU_SMC_CYCLE_T1 {NA} \ - CONFIG.PSU_SMC_CYCLE_T2 {NA} \ - CONFIG.PSU_SMC_CYCLE_T3 {NA} \ - CONFIG.PSU_SMC_CYCLE_T4 {NA} \ - CONFIG.PSU_SMC_CYCLE_T5 {NA} \ - CONFIG.PSU_SMC_CYCLE_T6 {NA} \ - CONFIG.PSU_VALUE_SILVERSION {3} \ - CONFIG.PSU__ACPU0__POWER__ON {1} \ - CONFIG.PSU__ACPU1__POWER__ON {1} \ - CONFIG.PSU__ACPU2__POWER__ON {1} \ - CONFIG.PSU__ACPU3__POWER__ON {1} \ - CONFIG.PSU__ACTUAL__IP {1} \ - CONFIG.PSU__ACT_DDR_FREQ_MHZ {533.333313} \ - CONFIG.PSU__AFI0_COHERENCY {0} \ - CONFIG.PSU__AFI1_COHERENCY {0} \ - CONFIG.PSU__AUX_REF_CLK__FREQMHZ {33.333} \ - CONFIG.PSU__CAN0_LOOP_CAN1__ENABLE {0} \ - CONFIG.PSU__CAN0__GRP_CLK__ENABLE {0} \ - CONFIG.PSU__CAN0__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__CAN1__GRP_CLK__ENABLE {0} \ - CONFIG.PSU__CAN1__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__CRF_APB__ACPU_CTRL__ACT_FREQMHZ {1199.999988} \ - CONFIG.PSU__CRF_APB__ACPU_CTRL__DIVISOR0 {1} \ - CONFIG.PSU__CRF_APB__ACPU_CTRL__FREQMHZ {1200} \ - CONFIG.PSU__CRF_APB__ACPU_CTRL__SRCSEL {APLL} \ - CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__ACT_FREQMHZ {667} \ - CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__FREQMHZ {667} \ - CONFIG.PSU__CRF_APB__AFI0_REF_CTRL__SRCSEL {DPLL} \ - CONFIG.PSU__CRF_APB__AFI0_REF__ENABLE {0} \ - CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__ACT_FREQMHZ {667} \ - CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__FREQMHZ {667} \ - CONFIG.PSU__CRF_APB__AFI1_REF_CTRL__SRCSEL {DPLL} \ - CONFIG.PSU__CRF_APB__AFI1_REF__ENABLE {0} \ - CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__ACT_FREQMHZ {667} \ - CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__FREQMHZ {667} \ - CONFIG.PSU__CRF_APB__AFI2_REF_CTRL__SRCSEL {DPLL} \ - CONFIG.PSU__CRF_APB__AFI2_REF__ENABLE {0} \ - CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__ACT_FREQMHZ {667} \ - CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__FREQMHZ {667} \ - CONFIG.PSU__CRF_APB__AFI3_REF_CTRL__SRCSEL {DPLL} \ - CONFIG.PSU__CRF_APB__AFI3_REF__ENABLE {0} \ - CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__ACT_FREQMHZ {667} \ - CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__FREQMHZ {667} \ - CONFIG.PSU__CRF_APB__AFI4_REF_CTRL__SRCSEL {DPLL} \ - CONFIG.PSU__CRF_APB__AFI4_REF__ENABLE {0} \ - CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__ACT_FREQMHZ {667} \ - CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__FREQMHZ {667} \ - CONFIG.PSU__CRF_APB__AFI5_REF_CTRL__SRCSEL {DPLL} \ - CONFIG.PSU__CRF_APB__AFI5_REF__ENABLE {0} \ - CONFIG.PSU__CRF_APB__APLL_CTRL__DIV2 {1} \ - CONFIG.PSU__CRF_APB__APLL_CTRL__FBDIV {72} \ - CONFIG.PSU__CRF_APB__APLL_CTRL__FRACDATA {0} \ - CONFIG.PSU__CRF_APB__APLL_CTRL__FRACFREQ {27.138} \ - CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL {PSS_REF_CLK} \ - CONFIG.PSU__CRF_APB__APLL_FRAC_CFG__ENABLED {0} \ - CONFIG.PSU__CRF_APB__APLL_TO_LPD_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRF_APB__APM_CTRL__ACT_FREQMHZ {1} \ - CONFIG.PSU__CRF_APB__APM_CTRL__DIVISOR0 {1} \ - CONFIG.PSU__CRF_APB__APM_CTRL__FREQMHZ {1} \ - CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__ACT_FREQMHZ {249.999998} \ - CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRF_APB__DBG_FPD_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__ACT_FREQMHZ {250} \ - CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__DIVISOR0 {5} \ - CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRF_APB__DBG_TRACE_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__ACT_FREQMHZ {249.999998} \ - CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRF_APB__DBG_TSTMP_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__DDR_CTRL__ACT_FREQMHZ {266.666664} \ - CONFIG.PSU__CRF_APB__DDR_CTRL__DIVISOR0 {4} \ - CONFIG.PSU__CRF_APB__DDR_CTRL__FREQMHZ {533} \ - CONFIG.PSU__CRF_APB__DDR_CTRL__SRCSEL {DPLL} \ - CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__ACT_FREQMHZ {599.999994} \ - CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__FREQMHZ {600} \ - CONFIG.PSU__CRF_APB__DPDMA_REF_CTRL__SRCSEL {APLL} \ - CONFIG.PSU__CRF_APB__DPLL_CTRL__DIV2 {1} \ - CONFIG.PSU__CRF_APB__DPLL_CTRL__FBDIV {64} \ - CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACDATA {0} \ - CONFIG.PSU__CRF_APB__DPLL_CTRL__FRACFREQ {27.138} \ - CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL {PSS_REF_CLK} \ - CONFIG.PSU__CRF_APB__DPLL_FRAC_CFG__ENABLED {0} \ - CONFIG.PSU__CRF_APB__DPLL_TO_LPD_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__ACT_FREQMHZ {24.576042} \ - CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR0 {16} \ - CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__FREQMHZ {25} \ - CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {RPLL} \ - CONFIG.PSU__CRF_APB__DP_AUDIO__FRAC_ENABLED {1} \ - CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__ACT_FREQMHZ {26.214445} \ - CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__FREQMHZ {27} \ - CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {RPLL} \ - CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__ACT_FREQMHZ {297.029588} \ - CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR0 {4} \ - CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__FREQMHZ {300} \ - CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} \ - CONFIG.PSU__CRF_APB__DP_VIDEO__FRAC_ENABLED {1} \ - CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__ACT_FREQMHZ {599.999994} \ - CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__FREQMHZ {600} \ - CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL {APLL} \ - CONFIG.PSU__CRF_APB__GPU_REF_CTRL__ACT_FREQMHZ {499.999995} \ - CONFIG.PSU__CRF_APB__GPU_REF_CTRL__DIVISOR0 {1} \ - CONFIG.PSU__CRF_APB__GPU_REF_CTRL__FREQMHZ {500} \ - CONFIG.PSU__CRF_APB__GPU_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__ACT_FREQMHZ {-1} \ - CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__DIVISOR0 {-1} \ - CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__FREQMHZ {-1} \ - CONFIG.PSU__CRF_APB__GTGREF0_REF_CTRL__SRCSEL {NA} \ - CONFIG.PSU__CRF_APB__GTGREF0__ENABLE {NA} \ - CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__ACT_FREQMHZ {250} \ - CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRF_APB__PCIE_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__SATA_REF_CTRL__ACT_FREQMHZ {250} \ - CONFIG.PSU__CRF_APB__SATA_REF_CTRL__DIVISOR0 {5} \ - CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__ACT_FREQMHZ {99.999999} \ - CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__DIVISOR0 {5} \ - CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__ACT_FREQMHZ {533.333328} \ - CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__DIVISOR0 {2} \ - CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ {533.333} \ - CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {DPLL} \ - CONFIG.PSU__CRF_APB__VPLL_CTRL__DIV2 {1} \ - CONFIG.PSU__CRF_APB__VPLL_CTRL__FBDIV {71} \ - CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACDATA {0.2871} \ - CONFIG.PSU__CRF_APB__VPLL_CTRL__FRACFREQ {300} \ - CONFIG.PSU__CRF_APB__VPLL_CTRL__SRCSEL {PSS_REF_CLK} \ - CONFIG.PSU__CRF_APB__VPLL_FRAC_CFG__ENABLED {1} \ - CONFIG.PSU__CRF_APB__VPLL_TO_LPD_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__ACT_FREQMHZ {499.999995} \ - CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ {500} \ - CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__ACT_FREQMHZ {500} \ - CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__FREQMHZ {500} \ - CONFIG.PSU__CRL_APB__AFI6_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__AFI6__ENABLE {0} \ - CONFIG.PSU__CRL_APB__AMS_REF_CTRL__ACT_FREQMHZ {51.724137} \ - CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR0 {29} \ - CONFIG.PSU__CRL_APB__AMS_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__AMS_REF_CTRL__FREQMHZ {50} \ - CONFIG.PSU__CRL_APB__AMS_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__ACT_FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__CAN0_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__ACT_FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__CPU_R5_CTRL__ACT_FREQMHZ {499.999995} \ - CONFIG.PSU__CRL_APB__CPU_R5_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__CPU_R5_CTRL__FREQMHZ {500} \ - CONFIG.PSU__CRL_APB__CPU_R5_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__ACT_FREQMHZ {180} \ - CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__FREQMHZ {180} \ - CONFIG.PSU__CRL_APB__CSU_PLL_CTRL__SRCSEL {SysOsc} \ - CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__ACT_FREQMHZ {249.999998} \ - CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRL_APB__DBG_LPD_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__ACT_FREQMHZ {1000} \ - CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__FREQMHZ {1000} \ - CONFIG.PSU__CRL_APB__DEBUG_R5_ATCLK_CTRL__SRCSEL {RPLL} \ - CONFIG.PSU__CRL_APB__DLL_REF_CTRL__ACT_FREQMHZ {1499.999985} \ - CONFIG.PSU__CRL_APB__DLL_REF_CTRL__FREQMHZ {1500} \ - CONFIG.PSU__CRL_APB__DLL_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__ACT_FREQMHZ {125} \ - CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR0 {12} \ - CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__FREQMHZ {125} \ - CONFIG.PSU__CRL_APB__GEM0_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__ACT_FREQMHZ {125} \ - CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR0 {12} \ - CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__FREQMHZ {125} \ - CONFIG.PSU__CRL_APB__GEM1_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__ACT_FREQMHZ {125} \ - CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR0 {12} \ - CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__FREQMHZ {125} \ - CONFIG.PSU__CRL_APB__GEM2_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__ACT_FREQMHZ {125} \ - CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR0 {12} \ - CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ {125} \ - CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__ACT_FREQMHZ {250} \ - CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR0 {4} \ - CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRL_APB__GEM_TSU_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__ACT_FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__ACT_FREQMHZ {99.999999} \ - CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__IOPLL_CTRL__DIV2 {0} \ - CONFIG.PSU__CRL_APB__IOPLL_CTRL__FBDIV {45} \ - CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACDATA {0} \ - CONFIG.PSU__CRL_APB__IOPLL_CTRL__FRACFREQ {27.138} \ - CONFIG.PSU__CRL_APB__IOPLL_CTRL__SRCSEL {PSS_REF_CLK} \ - CONFIG.PSU__CRL_APB__IOPLL_FRAC_CFG__ENABLED {0} \ - CONFIG.PSU__CRL_APB__IOPLL_TO_FPD_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__ACT_FREQMHZ {249.999998} \ - CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRL_APB__IOU_SWITCH_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__ACT_FREQMHZ {99.999999} \ - CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__LPD_LSBUS_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__ACT_FREQMHZ {499.999995} \ - CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__FREQMHZ {500} \ - CONFIG.PSU__CRL_APB__LPD_SWITCH_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__NAND_REF_CTRL__ACT_FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__NAND_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__NAND_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__NAND_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__ACT_FREQMHZ {500} \ - CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__FREQMHZ {500} \ - CONFIG.PSU__CRL_APB__OCM_MAIN_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__PCAP_CTRL__ACT_FREQMHZ {187.499998} \ - CONFIG.PSU__CRL_APB__PCAP_CTRL__DIVISOR0 {8} \ - CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ {200} \ - CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__PL0_REF_CTRL__ACT_FREQMHZ {99.999999} \ - CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__PL0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__PL1_REF_CTRL__ACT_FREQMHZ {20.000000} \ - CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR0 {25} \ - CONFIG.PSU__CRL_APB__PL1_REF_CTRL__DIVISOR1 {3} \ - CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ {20} \ - CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__PL2_REF_CTRL__ACT_FREQMHZ {50.000} \ - CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR0 {4} \ - CONFIG.PSU__CRL_APB__PL2_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__PL2_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__PL2_REF_CTRL__SRCSEL {RPLL} \ - CONFIG.PSU__CRL_APB__PL3_REF_CTRL__ACT_FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR0 {4} \ - CONFIG.PSU__CRL_APB__PL3_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__PL3_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__PL3_REF_CTRL__SRCSEL {RPLL} \ - CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__ACT_FREQMHZ {300} \ - CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR0 {5} \ - CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__FREQMHZ {300} \ - CONFIG.PSU__CRL_APB__QSPI_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__RPLL_CTRL__DIV2 {1} \ - CONFIG.PSU__CRL_APB__RPLL_CTRL__FBDIV {70} \ - CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACDATA {0.779} \ - CONFIG.PSU__CRL_APB__RPLL_CTRL__FRACFREQ {25} \ - CONFIG.PSU__CRL_APB__RPLL_CTRL__SRCSEL {PSS_REF_CLK} \ - CONFIG.PSU__CRL_APB__RPLL_FRAC_CFG__ENABLED {1} \ - CONFIG.PSU__CRL_APB__RPLL_TO_FPD_CTRL__DIVISOR0 {3} \ - CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__ACT_FREQMHZ {187.499998} \ - CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR0 {8} \ - CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__FREQMHZ {200} \ - CONFIG.PSU__CRL_APB__SDIO0_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__ACT_FREQMHZ {187.499998} \ - CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR0 {8} \ - CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ {200} \ - CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__ACT_FREQMHZ {187.499998} \ - CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR0 {8} \ - CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ {200} \ - CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__ACT_FREQMHZ {187.499998} \ - CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR0 {8} \ - CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__FREQMHZ {200} \ - CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__ACT_FREQMHZ {99.999999} \ - CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__UART0_REF_CTRL__ACT_FREQMHZ {99.999999} \ - CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__UART0_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__UART1_REF_CTRL__ACT_FREQMHZ {99.999999} \ - CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR0 {15} \ - CONFIG.PSU__CRL_APB__UART1_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ {100} \ - CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__ACT_FREQMHZ {249.999998} \ - CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__ACT_FREQMHZ {249.999998} \ - CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR0 {6} \ - CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__DIVISOR1 {1} \ - CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__FREQMHZ {250} \ - CONFIG.PSU__CRL_APB__USB1_BUS_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__ACT_FREQMHZ {20.000000} \ - CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR0 {5} \ - CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__DIVISOR1 {15} \ - CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ {20} \ - CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL {IOPLL} \ - CONFIG.PSU__CRL_APB__USB3__ENABLE {1} \ - CONFIG.PSU__CSUPMU__PERIPHERAL__VALID {1} \ - CONFIG.PSU__CSU_COHERENCY {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_0__ENABLE {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_0__ERASE_BBRAM {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_10__ENABLE {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_10__ERASE_BBRAM {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_11__ENABLE {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_11__ERASE_BBRAM {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_12__ENABLE {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_12__ERASE_BBRAM {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_1__ENABLE {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_1__ERASE_BBRAM {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_2__ENABLE {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_2__ERASE_BBRAM {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_3__ENABLE {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_3__ERASE_BBRAM {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_4__ENABLE {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_4__ERASE_BBRAM {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_5__ENABLE {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_5__ERASE_BBRAM {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_6__ENABLE {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_6__ERASE_BBRAM {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_7__ENABLE {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_7__ERASE_BBRAM {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_8__ENABLE {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_8__ERASE_BBRAM {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_9__ENABLE {0} \ - CONFIG.PSU__CSU__CSU_TAMPER_9__ERASE_BBRAM {0} \ - CONFIG.PSU__CSU__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__DDRC__ADDR_MIRROR {1} \ - CONFIG.PSU__DDRC__AL {0} \ - CONFIG.PSU__DDRC__BANK_ADDR_COUNT {3} \ - CONFIG.PSU__DDRC__BG_ADDR_COUNT {NA} \ - CONFIG.PSU__DDRC__BRC_MAPPING {ROW_BANK_COL} \ - CONFIG.PSU__DDRC__BUS_WIDTH {32 Bit} \ - CONFIG.PSU__DDRC__CL {NA} \ - CONFIG.PSU__DDRC__CLOCK_STOP_EN {0} \ - CONFIG.PSU__DDRC__COL_ADDR_COUNT {10} \ - CONFIG.PSU__DDRC__COMPONENTS {Components} \ - CONFIG.PSU__DDRC__CWL {NA} \ - CONFIG.PSU__DDRC__DDR4_ADDR_MAPPING {NA} \ - CONFIG.PSU__DDRC__DDR4_CAL_MODE_ENABLE {NA} \ - CONFIG.PSU__DDRC__DDR4_CRC_CONTROL {NA} \ - CONFIG.PSU__DDRC__DDR4_MAXPWR_SAVING_EN {NA} \ - CONFIG.PSU__DDRC__DDR4_T_REF_MODE {NA} \ - CONFIG.PSU__DDRC__DDR4_T_REF_RANGE {NA} \ - CONFIG.PSU__DDRC__DEEP_PWR_DOWN_EN {0} \ - CONFIG.PSU__DDRC__DEVICE_CAPACITY {8192 MBits} \ - CONFIG.PSU__DDRC__DIMM_ADDR_MIRROR {NA} \ - CONFIG.PSU__DDRC__DM_DBI {DM_NO_DBI} \ - CONFIG.PSU__DDRC__DQMAP_0_3 {0} \ - CONFIG.PSU__DDRC__DQMAP_12_15 {0} \ - CONFIG.PSU__DDRC__DQMAP_16_19 {0} \ - CONFIG.PSU__DDRC__DQMAP_20_23 {0} \ - CONFIG.PSU__DDRC__DQMAP_24_27 {0} \ - CONFIG.PSU__DDRC__DQMAP_28_31 {0} \ - CONFIG.PSU__DDRC__DQMAP_32_35 {0} \ - CONFIG.PSU__DDRC__DQMAP_36_39 {0} \ - CONFIG.PSU__DDRC__DQMAP_40_43 {0} \ - CONFIG.PSU__DDRC__DQMAP_44_47 {0} \ - CONFIG.PSU__DDRC__DQMAP_48_51 {0} \ - CONFIG.PSU__DDRC__DQMAP_4_7 {0} \ - CONFIG.PSU__DDRC__DQMAP_52_55 {0} \ - CONFIG.PSU__DDRC__DQMAP_56_59 {0} \ - CONFIG.PSU__DDRC__DQMAP_60_63 {0} \ - CONFIG.PSU__DDRC__DQMAP_64_67 {0} \ - CONFIG.PSU__DDRC__DQMAP_68_71 {0} \ - CONFIG.PSU__DDRC__DQMAP_8_11 {0} \ - CONFIG.PSU__DDRC__DRAM_WIDTH {32 Bits} \ - CONFIG.PSU__DDRC__ECC {Disabled} \ - CONFIG.PSU__DDRC__ECC_SCRUB {0} \ - CONFIG.PSU__DDRC__ENABLE {1} \ - CONFIG.PSU__DDRC__ENABLE_2T_TIMING {0} \ - CONFIG.PSU__DDRC__ENABLE_DP_SWITCH {0} \ - CONFIG.PSU__DDRC__ENABLE_LP4_HAS_ECC_COMP {0} \ - CONFIG.PSU__DDRC__ENABLE_LP4_SLOWBOOT {0} \ - CONFIG.PSU__DDRC__EN_2ND_CLK {0} \ - CONFIG.PSU__DDRC__FGRM {NA} \ - CONFIG.PSU__DDRC__FREQ_MHZ {1} \ - CONFIG.PSU__DDRC__LP_ASR {NA} \ - CONFIG.PSU__DDRC__MEMORY_TYPE {LPDDR 4} \ - CONFIG.PSU__DDRC__PARITY_ENABLE {NA} \ - CONFIG.PSU__DDRC__PER_BANK_REFRESH {0} \ - CONFIG.PSU__DDRC__PHY_DBI_MODE {0} \ - CONFIG.PSU__DDRC__PLL_BYPASS {0} \ - CONFIG.PSU__DDRC__PWR_DOWN_EN {0} \ - CONFIG.PSU__DDRC__RANK_ADDR_COUNT {1} \ - CONFIG.PSU__DDRC__RD_DQS_CENTER {0} \ - CONFIG.PSU__DDRC__ROW_ADDR_COUNT {15} \ - CONFIG.PSU__DDRC__SB_TARGET {NA} \ - CONFIG.PSU__DDRC__SELF_REF_ABORT {NA} \ - CONFIG.PSU__DDRC__SPEED_BIN {LPDDR4_1066} \ - CONFIG.PSU__DDRC__STATIC_RD_MODE {0} \ - CONFIG.PSU__DDRC__TRAIN_DATA_EYE {1} \ - CONFIG.PSU__DDRC__TRAIN_READ_GATE {1} \ - CONFIG.PSU__DDRC__TRAIN_WRITE_LEVEL {1} \ - CONFIG.PSU__DDRC__T_FAW {40} \ - CONFIG.PSU__DDRC__T_RAS_MIN {42} \ - CONFIG.PSU__DDRC__T_RC {63} \ - CONFIG.PSU__DDRC__T_RCD {10} \ - CONFIG.PSU__DDRC__T_RP {12} \ - CONFIG.PSU__DDRC__VENDOR_PART {OTHERS} \ - CONFIG.PSU__DDRC__VIDEO_BUFFER_SIZE {0} \ - CONFIG.PSU__DDRC__VREF {1} \ - CONFIG.PSU__DDR_HIGH_ADDRESS_GUI_ENABLE {0} \ - CONFIG.PSU__DDR_SW_REFRESH_ENABLED {0} \ - CONFIG.PSU__DDR__INTERFACE__FREQMHZ {266.500} \ - CONFIG.PSU__DEVICE_TYPE {EG} \ - CONFIG.PSU__DISPLAYPORT__LANE0__ENABLE {1} \ - CONFIG.PSU__DISPLAYPORT__LANE0__IO {GT Lane1} \ - CONFIG.PSU__DISPLAYPORT__LANE1__ENABLE {1} \ - CONFIG.PSU__DISPLAYPORT__LANE1__IO {GT Lane0} \ - CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__DLL__ISUSED {1} \ - CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30} \ - CONFIG.PSU__DP__LANE_SEL {Dual Lower} \ - CONFIG.PSU__DP__REF_CLK_FREQ {27} \ - CONFIG.PSU__DP__REF_CLK_SEL {Ref Clk1} \ - CONFIG.PSU__ENABLE__DDR__REFRESH__SIGNALS {0} \ - CONFIG.PSU__ENET0__FIFO__ENABLE {0} \ - CONFIG.PSU__ENET0__GRP_MDIO__ENABLE {0} \ - CONFIG.PSU__ENET0__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__ENET0__PTP__ENABLE {0} \ - CONFIG.PSU__ENET0__TSU__ENABLE {0} \ - CONFIG.PSU__ENET1__FIFO__ENABLE {0} \ - CONFIG.PSU__ENET1__GRP_MDIO__ENABLE {0} \ - CONFIG.PSU__ENET1__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__ENET1__PTP__ENABLE {0} \ - CONFIG.PSU__ENET1__TSU__ENABLE {0} \ - CONFIG.PSU__ENET2__FIFO__ENABLE {0} \ - CONFIG.PSU__ENET2__GRP_MDIO__ENABLE {0} \ - CONFIG.PSU__ENET2__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__ENET2__PTP__ENABLE {0} \ - CONFIG.PSU__ENET2__TSU__ENABLE {0} \ - CONFIG.PSU__ENET3__FIFO__ENABLE {0} \ - CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {0} \ - CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__ENET3__PTP__ENABLE {0} \ - CONFIG.PSU__ENET3__TSU__ENABLE {0} \ - CONFIG.PSU__EN_AXI_STATUS_PORTS {0} \ - CONFIG.PSU__EN_EMIO_TRACE {0} \ - CONFIG.PSU__EP__IP {0} \ - CONFIG.PSU__EXPAND__CORESIGHT {0} \ - CONFIG.PSU__EXPAND__FPD_SLAVES {0} \ - CONFIG.PSU__EXPAND__GIC {0} \ - CONFIG.PSU__EXPAND__LOWER_LPS_SLAVES {0} \ - CONFIG.PSU__EXPAND__UPPER_LPS_SLAVES {0} \ - CONFIG.PSU__FPDMASTERS_COHERENCY {0} \ - CONFIG.PSU__FPD_SLCR__WDT1__ACT_FREQMHZ {100.000000} \ - CONFIG.PSU__FPD_SLCR__WDT1__FREQMHZ {100.000000} \ - CONFIG.PSU__FPD_SLCR__WDT_CLK_SEL__SELECT {APB} \ - CONFIG.PSU__FPGA_PL0_ENABLE {1} \ - CONFIG.PSU__FPGA_PL1_ENABLE {1} \ - CONFIG.PSU__FPGA_PL2_ENABLE {0} \ - CONFIG.PSU__FPGA_PL3_ENABLE {0} \ - CONFIG.PSU__FP__POWER__ON {1} \ - CONFIG.PSU__FTM__CTI_IN_0 {0} \ - CONFIG.PSU__FTM__CTI_IN_1 {0} \ - CONFIG.PSU__FTM__CTI_IN_2 {0} \ - CONFIG.PSU__FTM__CTI_IN_3 {0} \ - CONFIG.PSU__FTM__CTI_OUT_0 {0} \ - CONFIG.PSU__FTM__CTI_OUT_1 {0} \ - CONFIG.PSU__FTM__CTI_OUT_2 {0} \ - CONFIG.PSU__FTM__CTI_OUT_3 {0} \ - CONFIG.PSU__FTM__GPI {0} \ - CONFIG.PSU__FTM__GPO {0} \ - CONFIG.PSU__GEM0_COHERENCY {0} \ - CONFIG.PSU__GEM1_COHERENCY {0} \ - CONFIG.PSU__GEM2_COHERENCY {0} \ - CONFIG.PSU__GEM3_COHERENCY {0} \ - CONFIG.PSU__GEM__TSU__ENABLE {0} \ - CONFIG.PSU__GEN_IPI_0__MASTER {APU} \ - CONFIG.PSU__GEN_IPI_10__MASTER {NONE} \ - CONFIG.PSU__GEN_IPI_1__MASTER {RPU0} \ - CONFIG.PSU__GEN_IPI_2__MASTER {RPU1} \ - CONFIG.PSU__GEN_IPI_3__MASTER {PMU} \ - CONFIG.PSU__GEN_IPI_4__MASTER {PMU} \ - CONFIG.PSU__GEN_IPI_5__MASTER {PMU} \ - CONFIG.PSU__GEN_IPI_6__MASTER {PMU} \ - CONFIG.PSU__GEN_IPI_7__MASTER {NONE} \ - CONFIG.PSU__GEN_IPI_8__MASTER {NONE} \ - CONFIG.PSU__GEN_IPI_9__MASTER {NONE} \ - CONFIG.PSU__GPIO0_MIO__IO {MIO 0 .. 25} \ - CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__GPIO1_MIO__IO {MIO 26 .. 51} \ - CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__GPIO2_MIO__IO {MIO 52 .. 77} \ - CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {1} \ - CONFIG.PSU__GPIO_EMIO_WIDTH {6} \ - CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE {0} \ - CONFIG.PSU__GPIO_EMIO__PERIPHERAL__IO {