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Is ADC being overclocked? #473
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Hi Richard,
Thanks for sharing this. Of course the basic initialization should observe
the limits in the specs.
Did you observe a performance impact after changing the ADC prescaler
settings, i.e., did you observe an offset of the average value, an impact
on the linearity error or different noise properties?
Thanks!
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I was poking around the ADC code today in mindev because I wanted to slow the CPU clock of a STM8S003 to power consumption but I still waned to do an ADC conversion.
If I understand this correctly the HSI clock has no prescaler giving a Fmaster of 16MHZ. When Fmaster feeds the ADC is is prescaled by 2 giving a ADC clock of 8MHZ. The maximum ADC clock is 6MHz but it is voltage dependent. It is only 4MHz at 3V.
Could the fix be to load ADC_CR1 with $20, instead of using #0, giving a prescaler of 4?
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